ADM8690 Analog Devices, ADM8690 Datasheet - Page 13

• Manufacturer Part Number: ADM8690
• Description: µP Supervisory Circuit, 8-Pin DIP
• Manufacturer: Analog Devices

Specifications of ADM8690

• Batt-backup-flg: Yes
• Product Description: uP Supv Ckt, Watchdog Timer, Backup Battery Switching, 4.65V Reset Trip Voltage, 8-Pin DIP & SOIC
• Reset Threshold (v): 4.65
• Min Reset Timeout (ms): 35
• Reset Output-stage: Active-Low/Push-Pull
• Backup-battery Switch: Yes
• Chip Enable Gating: ---
• Typ Watchdog Timeout (ms): 100,1600
• Package: DIP,SOIC
• Us Price 1000-4999: n/a

Data Sheet
WATCHDOG OUTPUT (WDO) (
The watchdog output ( WDO pin on the
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input.
below the reset threshold.
Figure 19. Internal Oscillator (1.6 Second Watchdog)
Figure 20. Internal Oscillator (100 ms Watchdog)
0 TO 500kHz
CLOCK
C
OSC
NC
NC
NC
Figure 17. External Clock Source
Figure 18. External Capacitor
WDO is also set high when V
8
8
7
7
8
7
OSC SEL
OSC IN
OSC SEL
OSC IN
8
7
OSC SEL
OSC IN
ADM8691/
ADM8691/
ADM8695
ADM8695
OSC SEL
OSC IN
ADM8691/
ADM8695
ADM8691/
ADM8691 ADM8695
ADM8695
ADM8691 ADM8695
/
/
CC
goes
Rev. C | Page 13 of 24
)
)
CE GATING AND RAM WRITE PROTECTION
(
The
that ensures the integrity of data in memory by preventing write
operations when V
( CE
inputs of CMOS RAM. When V
replica of CE
below the reset voltage threshold or V
CE
CE
backed-up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
invalid level. Similar protection of EEPROMs can be achieved
using the CE
LOW LINE
ADM8691 ADM8695
RESET
CE
OUT
OUT
IN
CE
ADM8691/ADM8695
V
OUT
and CE
CC
IN
high, independent of CE
typically drives the CE , CS , or write input of battery
OUT
IN
OUT
CE
/
V2
, with a 3 ns propagation delay. When V
IN
) can be used to control the chip enable or write
pin to drive the store or write inputs.
ADM8690/ADM8691/ADM8695
t
1
t 1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2 – V1
CC
ADM8691/
Figure 21. Chip Enable Gating
Figure 22. Chip Enable Timing
ADM8695
is at an invalid level. Two additional pins
V
V
CC
CC
LOW = 0
OK = 1
include memory protection circuitry
V1
)
IN
CC
.
is present, CE
BATT
V2
, an internal gate forces
t
1
CE
OUT
OUT
is a buffered
CC
is at an
CC
falls
V1