ADM1192 Analog Devices, ADM1192 Datasheet - Page 13

• Manufacturer Part Number: ADM1192
• Description: Digital Power Monitor with Clear Pin and ALERT Output
• Manufacturer: Analog Devices

Specifications of ADM1192

• Max Pos Supply (v): +26V
• Current Monitoring: 2
• Glitch Filter: Programmable Timer
• Clrb Pin: X
• Alert/alertb: ALERT
• Number Of I2c Addresses: 4
• Package: MSOP

WRITE EXTENDED COMMAND BYTE
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:
1.
2.
3.
4.
5.
6.
Table 9. ALERT_EN Register Operations
Bit
0
1
2
3
4
Table 10. ALERT_TH Register Operations
Bit
[7:0]
Table 11. CONTROL Register Operations
Bit
0
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address, followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends the register address byte. The MSB of this
byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Table 8). All other bits should be set to 0.
The slave asserts an acknowledge on SDA.
The master sends the extended command byte (refer to
Table 9, Table 10, and Table 11).
Default
0
Default
0
0
1
0
0
Default
FF
Name
SWOFF
Name
EN_ADC_OC1
EN_ADC_OC4
EN_OC_ALERT
EN_OFF_ALERT
CLEAR
Function
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
value corresponds to the top eight bits of the current channel data.
Function
LSB, forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Function
LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the
ALERT_TH register.
Enables the OC_ALERT register. If an overcurrent condition is present and the TIMER pin charges to 1.3 V, the
OC_ALERT register captures and latches this condition.
Enables an alert if the hot swap operation is turned off by an operation that writes the SWOFF bit high.
This allows a software override of the ALERT output and turns on a P-channel FET controlled by ALERT.
Clears the OC_ALERT and ADC_ALERT status bits in the status register. The value of these bits can
immediately change if the source of the alert is not cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.
Rev. B | Page 13 of 20
7.
8.
Table 9, Table 10, and Table 11 provide the details of each
extended register.
Table 8. Extended Register Addresses
A6
0
0
0
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
A5
0
0
0
1
S
A4
0
0
0
ADDRESS W A
SLAVE
2
A3
0
0
0
Figure 23. Write Extended Byte
3
A2
0
0
0
REGISTER
ADDRESS
4
A1
0
1
1
5
A
A0
1
0
1
EXTENDED
COMMAND
BYTE
6
Extended Register
ALERT_EN
ALERT_TH
CONTROL
7 8
A P
ADM1192