ADM1192 Analog Devices, ADM1192 Datasheet - Page 4

• Manufacturer Part Number: ADM1192
• Description: Digital Power Monitor with Clear Pin and ALERT Output
• Manufacturer: Analog Devices

Specifications of ADM1192

• Max Pos Supply (v): +26V
• Current Monitoring: 2
• Glitch Filter: Programmable Timer
• Clrb Pin: X
• Alert/alertb: ALERT
• Number Of I2c Addresses: 4
• Package: MSOP

ADM1192
Parameter
SETV PIN
TIMER PIN
ALERT PIN
ADR PIN
I
1
2
3
4
2
Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see the
specifications for the Current Sense Absolute Accuracy parameter).
These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see the
specifications for the Voltage Sense Accuracy parameter).
Time between the receipt of the command byte and the actual ADC result being placed in the register.
C TIMING
Overcurrent Trip Threshold
Overcurrent Trip Gain, V
Input Current, I
Glitch Filter, t
Pull-Up Current (Overcurrent Fault), I
Pull-Down Current, I
Pin Threshold High, V
Output Low Voltage, V
Input Current, I
Set Address to 00, V
Set Address to 01, R
Set Address to 10, I
Set Address to 11, V
Input Current for 00 Decode, I
Input Current for 11 Decode, I
Low Level Input Voltage, V
High Level Input Voltage, V
Low Level Output Voltage on SDA, V
Output Fall Time on SDA from V
Maximum Width of Spikes Suppressed by
Input Current, I
Input Capacitance on SDA/SCL
SCL Clock Frequency, f
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for Repeated Start Condition, t
SDA Output Data Hold Time, t
Setup Time for a Stop Condition, t
Bus Free Time Between a Stop and a Start
Capacitive Load for Each Bus Line
Input Filtering on SDA Pin and SCL Pin
Driving a Logic Low Output
Condition, t
SETVGLITCH
BUF
SETVLEAK
ALERT
I
, on SDA/SCL When Not
ADRHIGHZ
ADRLOWV
ADRLOWZ
ADRHIGHV
TIMERDN
TIMERH
ALERTOL
SCL
SETV
IL
IH
/(V
ADRLOW
ADRHIGH
HD;DAT
CC
IHMIN
− V
SU;STO
SENSE
to V
OL
TIMERUPOC
)
ILMAX
SU;STA
Min
49.5
−1
−46
1.275
−1
0
80
−0.3
2
−40
0.7 V
20 + 0.1 C
50
−10
600
1300
600
100
600
1300
98
BUS
BUS
Rev. B | Page 4 of 20
Typ
100
50
18
3
−62
100
1.3
0.05
1
120
−25
3
5
Max
102
50.5
+1
−78
1.325
0.1
1.5
+1
0.8
160
+0.3
5.5
6
0.3 V
0.4
250
250
+10
400
900
400
BUS
Unit
mV
mV
μA
μs
μA
μA
V
V
mA
μA
V
kΩ
μA
V
μA
μA
V
V
V
ns
ns
μA
pF
kHz
ns
ns
ns
ns
ns
ns
pF
Conditions
V
V
V
V
(18.125 × V
Normal operation, V
TIMER rising
I
I
V
Low state
Resistor to ground state, load pin with
specified resistance for 01 decode
Open state, maximum load allowed on
ADR pin for 10 decode
High state
V
V
I
C
ALERT
ALERT
OL
SETV
SETV
SETV
SETV
ALERT
ADR
ADR
BUS
= 3 mA
= bus capacitance from SDA to GND
= 0 V to 0.8 V
= 2.0 V to 5.5 V
= 1.8 V
= 0.9 V
= 0.9 V to 1.9 V
= 0.9 V to 1.9 V
= −100 μA
= −2 mA
= V
CC
; ALERT asserted
SENSE
) > V
SETV
TIMER
, V
= 1 V
TIMER
= 1 V