ADM1168 Analog Devices, ADM1168 Datasheet
ADM1168
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ADM1168 Summary of contents
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... The ADM1168 is controlled via configuration data that can be programmed into an EEPROM. The whole configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc ...
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... Fault and Status Reporting........................................................ 17 Nonvolatile Black Box Fault Recording................................... 17 Black Box Writes with No External Supply ............................ 18 Applications Diagram .................................................................... 19 Communicating with the ADM1168........................................... 20 Configuration Download at Power-Up................................... 20 Updating the Configuration ..................................................... 20 Updating the Sequencing Engine............................................. 21 Internal Registers........................................................................ 21 ...
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... GPI SIGNAL CONDITIONING SFD GPI SIGNAL CONDITIONING SEQUENCING ENGINE SFD SFD SFD REG 5.25V CHARGE PUMP GND VCCP Figure 2. Detailed Block Diagram Rev Page ADM1168 A0 OSC EEPROM CONFIGURABLE OUTPUT DRIVER PDO1 (HV) PDO2 PDO3 PDO4 PDO5 CONFIGURABLE OUTPUT DRIVER PDO6 (HV) ...
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... ADM1168 SPECIFICATIONS 3 14 VPx = 3 6.0 V Table 1. Parameter POWER SUPPLY ARBITRATION VH, VPx VPx VH VDDCAP C VDDCAP POWER SUPPLY Supply Current VPx Additional Currents All PDOx FET Drivers On Current Available from VDDCAP EEPROM Erase Current SUPPLY FAULT DETECTORS VH Pin Input Impedance Input Attenuator Error ...
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... VDDCAP = 4. 2.0 V 0 OUT See Figure 27 400 kHz 1.3 μs 0.6 μs 0.6 μs 0.6 μs 1.3 μs 0.6 μs 300 ns 300 ns 100 ns 250 ns 1 μ μs Rev Page ADM1168 & 25°C, if known logic state is required A = −3.0 mA ...
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... ADM1168 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltage on VH Pin Voltage on VPx Pins Voltage on VXx Pins Voltage on A0, A1 Pins Voltage on REFOUT Pin Voltage on VDDCAP, VCCP Pins Voltage on PDOx Pins Voltage on SDA, SCL Pins Voltage on GND, AGND, PDOGND, REFGND Pins Input Current at Any Pin ...
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... In a typical application, all ground pins are connected together VX1 PDO1 PIN 1 VX2 PDO2 INDICATOR VX3 PDO3 ADM1168 VX4 PDO4 VP1 PDO5 TOP VIEW (Not to Scale) VP2 PDO6 VP3 PDO7 VH PDO8 CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3. Pin Configuration Rev Page ADM1168 ...
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... ADM1168 TYPICAL PERFORMANCE CHARACTERISTICS (V) VP1 Figure 4. V vs. V VDDCAP (V) VH Figure 5. V vs. V VDDCAP 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 (V) VP1 Figure 6. I vs. V (VP1 as Supply) VP1 VP1 VP1 12 14 ...
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... LOAD 2.058 2.053 VP1 = 5V 2.048 2.043 2.038 5 6 –40 LOAD Rev Page ADM1168 VP1 = 5V VP1 = (µA) LOAD Figure 12. V (Weak Pull-Up to VPx) vs. I PDO1 LOAD VP1 = 3.0V VP1 = 4.75V – TEMPERATURE (°C) Figure 13. REFOUT vs. Temperature ...
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... A supply comparator chooses the highest input to provide the on-chip supply. There is minimal switching loss with this architecture (~0.2 V), resulting in the ability to power the ADM1168 from a supply as low as 3.0 V. Note that the supply on the VXx pins cannot be used to power the device. An external capacitor to GND is required to decouple the on-chip supply from noise ...
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... Table 6 shows the details of each input. PROGRAMMING THE SUPPLY FAULT DETECTORS The ADM1168 can have up to eight SFDs on its eight input channels. These highly programmable reset generators enable the supervision eight supply voltages. The supplies can be as low as 0 ...
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... ADM1168 INPUT COMPARATOR HYSTERESIS The UV and OV comparators shown in Figure 16 are always monitoring VPx. To avoid chatter (multiple transitions when the input is very close to the set threshold level), these comparators have digitally programmable hysteresis. The hysteresis can be programmed up to the values shown in Table 6. ...
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... Thus, potentially any supply can be divided down into the input range of the VXx pin and supervised. This enables the ADM1168 to monitor other supplies, such as +24 V, +48 V, and − additional supply supervision function is available when the VXx pins are selected as digital inputs ...
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... All of the internal registers in an unprogrammed ADM1168 device from the factory are set to 0. Because of this, the PDOx pins are pulled to GND by a weak (20 kΩ), on-chip, pull-down resistor. As the input supply to the ADM1168 ramps up on VPx or VH, all PDOx pins behave as follows: • ...
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... SEQUENCING ENGINE OVERVIEW The ADM1168 SE provides the user with powerful and flexible control of sequencing. The SE implements a state machine control of the PDO outputs with state changes conditional on input events. SE programs can enable complex control of boards such as power-up and power-down sequence control, fault event handling, and interrupt generation on warnings ...
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... ADM1168 SEQUENCING ENGINE APPLICATION EXAMPLE The application in this section demonstrates the operation of the SE. Figure 21 shows how the simple building block of a single SE state can be used to build a power-up sequence for a three- supply system. Table 8 lists the PDO outputs for each state in the same SE implementation. In this system, a good 5 V supply on the VP1 pin and the VX1 pin held low are the triggers required to start a power-up sequence ...
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... Each time the sequence engine enters that state, a fault record is written into EEPROM. The fault record provides a snapshot of the entire ADM1168 state at the point in time when the last state was exited, just prior to entering the designated black box write state. A fault record contains the following information: • ...
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... Typically, it takes write to the eight bytes of a fault record. If the ADM1168 is powered using supply on the VH pin, then a UV threshold can be set and used as the state machine trigger to start writing a fault record to EEPROM. The higher the ...
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... VX2 VX3 PWRGD PDO6 SIGNAL VALID PDO7 VX4 PDO8 VCCP VDDCAP REFOUT GND 10µF 10µF Figure 23. Applications Diagram Rev Page 12V OUT 5V OUT 3V OUT IN DC-TO-DC1 EN OUT 3.3V OUT IN DC-TO-DC2 EN OUT 1.25V OUT IN DC-TO-DC3 EN OUT 1.25V OUT 3.3V OUT IN LDO EN OUT 0.9V OUT ADM1168 ...
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... SFD, changing the fault output of an SFD, or adjusting the rise time delay of one of the PDOs. The ADM1168 provides several options that allow the user to update the configuration over the SMBus interface. The following three options are controlled in the UPDCFG register. ...
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... Address Pointer Register The address pointer register contains the address that selects one of the other internal registers. When writing to the ADM1168, the first byte of data is always a register address that is written to the address pointer register. Configuration Registers The configuration registers provide control and configuration for various operating parameters of the ADM1168 ...
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... Therefore, access to the ADM1168 is restricted until the download is complete. Identifying the ADM1168 on the SMBus The ADM1168 has a 7-bit serial bus slave address (see Table 9). The device is powered up with a default serial bus address. The five MSBs of the address are set to 10001; the two LSBs are determined by the logical states of Pin A1 and Pin A0 ...
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... ACK. BY MASTER FRAME N DATA BYTE HD;STA t t HIGH SU;STA t SU;DAT S Figure 27. Serial Bus Timing Diagram Rev Page ADM1168 9 D0 ACK. BY SLAVE ACK. BY STOP SLAVE BY MASTER 9 D0 ACK. BY MASTER STOP NO ACK. BY MASTER t SU ...
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... The slave asserts ACK on SDA. 10. The master asserts a stop condition on SDA to end the transaction. In the ADM1168, the write byte/word protocol is used for three purposes: • To write a single byte of data to the RAM. In this case, the command byte is RAM Address 0x00 to RAM Address 0xDF, and the only data byte is the actual data, as shown in Figure 30 ...
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... A DATA the ADM1168, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/ word operation, as shown in Figure 33 COMMAND 0xFC ...
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... In a block read operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously. In the ADM1168, this is done by a send byte operation to set a RAM address write byte/word operation to set an EEPROM address. The block read operation itself consists of ...
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... Figure 37. 32-Lead Low Profile Quad Flat Package [LQFP] (ST-32-2) Dimensions shown in millimeters Package Description 32-Lead Low Profile Quad Flat Package [LQFP] 32-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Rev Page 9.00 BSC PIN 1 7.00 BSC SQ TOP VIEW (PINS DOWN 0.45 0.80 0.37 BSC 0.30 Package Option ST-32-2 ST-32-2 ADM1168 ...
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... ADM1168 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09474-0-4/11(0) Rev Page ...