ADUC7060 Analog Devices, ADUC7060 Datasheet - Page 62

• Manufacturer Part Number: ADUC7060
• Description: Low-Power, Precision Analog Microcontroller, Dual ?-? ADCs, Flash/EE, ARM7TDMI
• Manufacturer: Analog Devices

Specifications of ADUC7060

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 10
• Sram (bytes): 4096Bytes
• Gpio Pins: 14
• Adc # Channels: 10
• Other: 14 Bit DAC,PWM

ADuC7060/ADuC7061
Table 68. IRQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
Priority Registers
The interrupt priority registers, IRQP0, IRQP1, and IRQP2,
allow each interrupt source to have its priority level configured
for a level between 0 and 7. Level 0 is the highest priority level.
IRQP0 Register
Name:
Address:
Default value:
Access:
Table 69. IRQP0 MMR Bit Designations
Bit
31:27
26:24
23
22:20
19
18:16
15
14:12
11:7
6:4
3:0
Access
Read
only
Read
only
Read
only
Reserved
Name
Reserved
T3PI
Reserved
T2PI
Reserved
T1PI
Reserved
T0PI
Reserved
SWINTP
Reserved
IRQP0
0xFFFF0020
0x00000000
Read and write
Initial
Value
0
0
0
0
Description
Reserved bits.
A priority level of 0 to 7 can be set for
Timer3.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer2.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer1.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer0.
Reserved bits.
A priority level of 0 to 7 can be set for the
software interrupt source.
Interrupt 0 cannot be prioritized.
Description
Always read as 0.
IRQBASE register value.
Highest priority IRQ source. This
is a value between 0 to 19 repre-
senting the possible interrupt
sources. For example, if the highest
currently active IRQ is Timer1, then
these bits are [01000].
Reserved bits.
Rev. C | Page 62 of 108
IRQP1 Register
Name:
Address:
Default value:
Access:
Table 70. IRQP1 MMR Bit Designations
Bit
31
30:28
27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7:0
IRQP2 Register
Name:
Address:
Default value:
Access:
Table 71. IRQP2 MMR Bit Designations
Bit
31:15
14:12
11
10:8
7
6:4
3
2:0
IRQ1PI
IRQ0PI
UARTPI
IRQ3PI
Name
Reserved
I2CMPI
Reserved
Reserved
Reserved
SPIMPI
Reserved
Reserved
ADCPI
Reserved
Name
Reserved
Reserved
IRQ2PI
Reserved
SPISPI
Reserved
I2CSPI
IRQP1
0xFFFF0024
0x00000000
Read and write
IRQP2
0xFFFF0028
0x00000000
Read and write
Description
Reserved bit.
A priority level of 0 to 7 can be set for I
master.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
master.
Reserved bit.
A priority level of 0 to 7 can be set for UART.
Reserved bit.
A priority level of 0 to 7 can be set for the
ADC interrupt source.
Reserved bits.
Description
Reserved bit.
A priority level of 0 to 7 can be set for IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
slave.
Reserved bit.
A priority level of 0 to 7 can be set for I
slave.
2
2
C
C