ADUC7022 Analog Devices, ADUC7022 Datasheet - Page 70

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ADUC7022

Manufacturer Part Number
ADUC7022
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7022

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
8192Bytes
Gpio Pins
13
Adc # Channels
10

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Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADuC7019/20/21/22/24/25/26/27/28/29
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
Table 117. SPISTA Register
Name
SPISTA
SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4
of this register generates an interrupt. Bit 6 of the SPICON
register determines which bit generates the interrupt.
Table 118. SPISTA MMR Bit Descriptions
Bit
7:6
5
4
3
2
1
0
Table 123. SPICON MMR Bit Descriptions
Bit
15:13
12
11
10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
SPIRX data register overflow status bit. Set if SPIRX is
overflowing. Cleared by reading the SPIRX register.
SPIRX data register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading the SPIRX register.
SPIRX data register full status bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading the SPIRX register.
SPITX data register underflow status bit. Set auto-
matically if SPITX is underflowing. Cleared by writing in
the SPITX register.
SPITX data register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
SPITX data register empty status bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
Description
Reserved
Continuous transfer enable
Loop back enable
Slave output enable
Slave select input enable
SPIRX overflow overwrite enable
SPITX underflow mode
Transfer and interrupt mode
LSB first transfer enable bit
Reserved
Serial clock polarity mode bit
Serial clock phase mode bit
Master mode enable bit
SPI enable bit
Address
0xFFFF0A00
Default Value
0x00
Function
N/A
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid
data is available in the TX register. CS is asserted and remains asserted for the duration of each
8-bit serial transfer until TX is empty. Cleared by user to disable continuous transfer. Each
transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a
new transfer is initiated after a stall period.
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Set by user to enable the slave output enable. Cleared by user to disable slave output enable.
Set by user in master mode to enable the output. Cleared by user to disable master output.
Set by user, the valid data in the RX register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
Set by user to transmit 0. Cleared by user to transmit the previous data.
Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs only when TX is
empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs only
when RX is full.
Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user,
the serial clock pulses at the end of each serial bit transfer.
Set by user to enable master mode. Cleared by user to enable slave mode.
Set by user to enable the SPI. Cleared by user to disable the SPI.
Access
R
Rev. D | Page 70 of 96
Table 119. SPIRX Register
Name
SPIRX
SPIRX is an 8-bit, read-only receive register.
Table 120. SPITX Register
Name
SPITX
SPITX is an 8-bit, write-only transmit register.
Table 121. SPIDIV Register
Name
SPIDIV
SPIDIV is an 8-bit, serial clock divider register.
Table 122. SPICON Register
Name
SPICON
SPICON is a 16-bit control register.
Address
0xFFFF0A04
Address
0xFFFF0A08
Address
0xFFFF0A0C
Address
0xFFFF0A10
Default Value
0x00
Default Value
0x00
Default Value
0x1B
Default Value
0x0000
Access
R
Access
W
Access
R/W
Access
R/W

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