ADP5034 Analog Devices, ADP5034 Datasheet - Page 21

• Manufacturer Part Number: ADP5034
• Description: Dual 3 MHz, 1200mA Buck Regulator with Two 300 mA LDOs
• Manufacturer: Analog Devices

Data Sheet
LDO EXTERNAL COMPONENT SELECTION
Feedback Resistors
For the adjustable model, the maximum value of Rb is not to
exceed 200 kΩ (see Figure 48).
Output Capacitor
The ADP5034 LDOs are designed for operation with small, space-
saving ceramic capacitors, but function with most commonly
used capacitors as long as care is taken with the ESR value. The
ESR of the output capacitor affects stability of the LDO control
loop. A minimum of 0.70 μF capacitance with an ESR of 1 Ω
or less is recommended to ensure that stability of the ADP5034.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP5034 to large
changes in load current.
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN3 and VIN4 to ground
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source imped-
ance is encountered. If greater than 1 μF of output capacitance
is required, increase the input capacitor to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5034 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempera-
ture range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended for best perfor-
mance. Y5V and Z5U dielectrics are not recommended for use
with any LDO because of their poor temperature and dc bias
characteristics.
Figure 51 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a capa-
citor is strongly influenced by the capacitor size and voltage rating.
In general, a capacitor in a larger package or with higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera-
ture range and is not a function of package or voltage rating.
Rev. A | Page 21 of 28
Use the following equation to determine the worst-case capa-
citance accounting for capacitor variation over temperature,
component tolerance, and voltage:
where:
C
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
Substituting these values into the following equation,
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5034, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
BIAS
1.2
1.0
0.8
0.6
0.4
0.2
0
C
C
is the effective capacitance at the operating voltage.
0
EFF
EFF
= C
= 0.85 μF × (1 − 0.15) × (1 − 0.1) = 0.65 μF
Figure 51. Capacitance vs. Voltage Characteristic
BIAS
1
× (1 − TEMPCO) × (1 − TOL)
BIAS
is 0.85 μF at 1.8 V as shown in Figure 51.
DC BIAS VOLTAGE (V)
2
3
4
5
ADP5034
6