ADP5034 Analog Devices, ADP5034 Datasheet - Page 24
Manufacturer Part Number
Dual 3 MHz, 1200mA Buck Regulator with Two 300 mA LDOs
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5034 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines. Also, refer to the
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Rev. A | Page 24 of 28
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
Connect VIN1, VIN2, and AVIN together close to the IC
using short tracks.