ADP2114 Analog Devices, ADP2114 Datasheet - Page 23

• Manufacturer Part Number: ADP2114
• Description: Configurable, Dual 2 A/Single 4 A, Synchronous Step-Down DC-to-DC Regulator
• Manufacturer: Analog Devices

HICCUP MODE CURRENT LIMIT
The ADP2114 features a hiccup mode current limit
implementation. When the peak inductor current exceeds
the preset current limit for more than eight consecutive clock
cycles, the hiccup mode current limit condition occurs. The
channel then goes to sleep for 6.8 ms (at a 600 kHz switching
frequency), which is enough time for the output to discharge
and the average power dissipation to reduce. It then wakes up
with a soft start period (see Figure 69). If the current limit
condition is triggered again, the channel goes to sleep and
wakes up after 6.8 ms. The current limits for the two channels
are programmed by configuring the OPCFG pin (see Table 7).
For the 2 A/2 A option, the output current limit is set to 3.3 A
per output. For the 3 A/1 A option, the current limits are set to
4.5 A and 1.9 A for V
THERMAL OVERLOAD PROTECTION
The ADP2114 has an internal temperature sensor that monitors
the junction temperature. High current going into the switches
or a hot printed circuit board (PCB) can cause the junction
temperature of the ADP2114 to rise rapidly. When the junction
temperature reaches approximately 150°C, the ADP2114 goes
into thermal shutdown and the converter is turned off. When the
junction temperature drops below 125°C, the ADP2114 resumes
normal operation after the soft start sequence.
4
2
3
CH3 5.0V
CH2 1.0V
CH4 2A
OUT1
Figure 69. Hiccup Mode
INDUCTOR
CURRENT
and V
V
SW
OUT
M2.0ms
OUT2
, respectively.
A CH4
1.72A
Rev. 0 | Page 23 of 40
MAXIMUM DUTY CYCLE OPERATION
As the input voltage drops and approaches the output voltage,
the ADP2114 smoothly transitions to maximum duty cycle
operation, maintaining the low-side, N-channel MOSFET switch
on for the minimum off time. In maximum duty cycle operation,
the output voltage dips below regulation because the output
voltage is the product of the input voltage and the maximum
duty cycle limitation. The maximum duty cycle limit is a
function of the switching frequency and the input voltage,
as shown in Figure 72.
SYNCHRONIZATION
The ADP2114 can be synchronized to an external clock such
that the two channels operate at a switching frequency that is
half the input synchronization clock. The SYNC/CLKOUT pin
can be configured as an input SYNC pin or an output CLKOUT
pin through the SCFG pin, as shown in Table 6. Through the input
SYNC pin, the ADP2114 can be synchronized to an external clock
such that the two channels switch at half the external clock, 180°
out of phase. Through the output CLKOUT pin, the ADP2114
provides an output clock that is twice the switching frequency of
the channels and 90° out of phase. Therefore, a single ADP2114
configured for the CLKOUT option acts as the master converter
and provides an external clock for all other dc-to-dc converters
(including other ADP2114s). These other converters are configured
as slaves that accept an external clock and synchronize to it.
This clock distribution approach synchronizes all dc-to-dc
converters in the system and prevents beat harmonics that
can lead to EMI issues.
The ADP2114 has been optimized to power high performance
signal chain circuits. The slew rate of the switch node is
controlled by the size of the driver devices. Fast slewing of the
switch node is desirable to minimize transition losses but can
lead to serious EMI issues due to parasitic inductance. Therefore,
the slew rate of the drivers has been optimized such that the
ADP2114 can match the performance of the low dropout
regulators in supplying sensitive signal chain circuits while
providing excellent power efficiency.
ADP2114