ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 22

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

ADAU1442/ADAU1445/ADAU1446
Table 9. PLL Modes
DSP Core Rate
Normal
Dual
Quad
1
2
If the normal DSP core rate (f
then f
The PLL divider is set by the PLLx pins.
S,DUAL
is 96 kHz and f
1
Input to MCLK
(XTALI Pin)
64 × f
128 × f
256 × f
384 × f
512 × f
32 × f
64 × f
128 × f
192 × f
256 × f
16 × f
32 × f
64 × f
96 × f
128 × f
S,QUAD
XTALI
S,NORMAL
is 192 kHz.
S,NORMAL
S,DUAL
S,DUAL
S,QUAD
S,QUAD
S,QUAD
S,QUAD
S,NORMAL
S,NORMAL
S,NORMAL
S,NORMAL
S,DUAL
S,DUAL
S,DUAL
S,QUAD
f
) is 44.1 kHz, the dual DSP core rate (f
S,NORMAL
f
S,DUAL
f
S,QUAD
× 32, 64, 128, 192, 256
× 64, 128, 256, 384, 512
× 16, 32, 64, 96, 128
PLL2
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
PLL MODE PINS
PLL1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
SELECT THE
PLL DIVIDER
PLL DIVIDER
(1, 2, 4, 6, 8)
Figure 10. Master Clock Signal Flow
÷
S,DUAL
Rev. C | Page 22 of 92
PLL0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
f
) is 88.2 kHz, and the quad DSP core rate (f
S,NORMAL
f
f
S,QUAD
S,DUAL
× 32
PLL
Divider
1
2
4
6
8
1
2
4
6
8
1
2
4
6
8
× 16
× 64
CORE CLOCK
MULTIPLIER
2
×
f
Core Clock
Multiplier
56
56
56
56
56
56
56
56
56
56
56
56
56
56
56
S,NORMAL
f
f
S,DUAL
S,QUAD
× 1792
× 896
× 3584
(NORMAL, DUAL, QUAD)
REGISTER 0xE220
DSP CORE RATE
SELECTS THE
S,QUAD
Core Clock
(f
3584 × f
3584 × f
3584 × f
3584 × f
3584 × f
1792 × f
1792 × f
1792 × f
1792 × f
1792 × f
896 × f
896 × f
896 × f
896 × f
896 × f
CORE
DSP
CORE
) is 176.4 kHz. Likewise, if f
)
S,QUAD
S,QUAD
S,QUAD
S,QUAD
S,QUAD
S,NORMAL
S,NORMAL
S,NORMAL
S,NORMAL
S,NORMAL
S,DUAL
S,DUAL
S,DUAL
S,DUAL
S,DUAL
Instructions per
Sample
3584
3584
3584
3584
3584
1792
1792
1792
1792
1792
896
896
896
896
896
S,NORMAL
is 48 kHz,