ADAU1445 Analog Devices, ADAU1445 Datasheet - Page 67

• Manufacturer Part Number: ADAU1445
• Manufacturer: Analog Devices

Specifications of ADAU1445

• Instructions/cycles: 3584
• Digital I/o Channels: 24/24
• Analog I/o Channels: 0/0
• Product Description: Digital audio processor with flexible audio routing matrix, 8 × 2-channel ASRC

Auxiliary Outputs—Set Enable Mod
(Address 0xE0C8)
Tab
Bit
Position
[15:2]
[1:0]
This registe
multipurpose pins
more in
Setting
off on r
may be
S/PDIF lock bit to g
outputs
bit must be activate
Hot En
informa
S/PDIF Lock Bit Detection Register (Addr ss 0xE0C9)
Table 60. Bit Descriptions of Register 0xE0C9
Bit
Position
[15:1]
0
This read-only register
loc
Se
Table
Bit
Position
[15:1]
0
t Hot Enable Regi
k bit.
le 59. Bit
61. Bit Descrip
able
eset) is usef
Bits[1:0] of
. W
inte
for
tio
n).
mation see the Enable S/PDIF
hen th S/PDIF stream i
rrupte unexpectedly. An interr
r cont ls when the S/PDIF s
Regist r (Address 0xE0
Des
Reserved
Auxiliary outputs enable mode
00 = au
01 = au
10 = au
(They
bit is
lock b t is 0.)
Reserved
Description
S/PDIF input lock bit (read only)
0 = no valid input stream
1 = successful lock to input stream
Descriptions of Register 0xE0C8
Description
Reserved
Hot enable bit
0 = hot enable inactive
1 = hot enable active
cri
1
ro
e
,
d
e
s
i
ul for situations in w
ption
and switch off as soon as
when the S/PD
witch on as soon as the ho
Register 0xE0C8 to 1
d to restore
xiliary outputs are alw
xiliary outputs are alw
xiliary outputs
o low, which in
tions of Register 0xE0C
ster (Addre
shows the s
the auxiliary outputs (see the Set
IF to I
are off on reset.
tatus of the S/PDIF input
ss 0xE0CA)
CA) sectio
s recovere
turn disables the auxiliary
hich th
e Register
0 (au
2
tream
S mode is active. For
ays off
ays
to I
the S/
up
t e
on.
xiliary outputs are
d, the hot enable
2
e
n for more
S Output section
tion causes the
nable
e S/PDIF stream
A
is active on the
.
PDIF
Defa
01
Default
0
Rev. C | Page 67 of 92
ult
.
This register allows the hot enable bit to be set, which
auxiliary outputs whe
outputs are off on a reset (that is, Bits[1:0] of Register
set to
that the S/ DIF receiver lo
Auxilia
(A
R
Table
Bit
Position
[15:1]
0
This read-only
outputs.
S/PDIF
Table 6
Bit
Position
[15:1]
0
This register controls the behavior of the S/PDIF receiver in the
event of a loss of lock to the input stream. A loss of lock can
arise when there is severe noise or jitter on the S/PDIF input
stream, re ndering it unrecognizable to the receiver. In the
default mode, such an event disables the S/PDIF receiver,
causing it to stop outputting frame sync pulses. T
caus
resume un l lock is regain
When
frame sy
c
su
lo
T
in
Ther
register should be used only when audio recovery is required.
In general, a loss-of-lock event is much shorter than an ASRC
mute or unmute ramp.
ompromise
ead Ena
he S/PDIF
tegrity well
ck is regai
ch a case,
ddress 0
es the target ASRC to be muted. Frame sync pulses do not
efore, even in cases of extreme signal degradation, this
10). The hot enable bit is set to 0 automatically in the event
62. Bit Descriptions of Register 0xE0CB
the re
ry O
3. Bit Descripti
Loss-of-Lock B
nc p
P
ble Auxiliary Output Register
ti
xE0C8) section.
utputs—S
ned.
the S/PDIF re
ADAU1442/ADAU1445/ADAU1446
gister is se
d and the au
receiver is robust and can recover streams
Description
Reserved
S/PDIF loss-of-lock behavior
0 = S/PDIF disable on loss of lock
1 = S/PDIF ignore loss of lock
ulses, even if
below the st
Description
Reserved
Read enable auxiliary output (read only)
0 = S/PDIF auxiliary outputs disabled
1 = S/PDIF auxiliary outputs enabled
register sh
n they are configured so that the auxiliary
et Enable Mode Register
t to 1, the S/PDIF receiver always outputs
ons of
andards of the AES/EBU specification.
ehavi
dio samples cannot be recovere . In
ses lock. For more information, s
ows the status of the S/PDIF auxiliary
ceiver data output remains at 0 ntil
the integrity of the S/PDIF str
ed.
Register 0
or Register (Address 0xE0CC)
xE0CC
(Address 0xE0CB)
his in turn
0xE0C8 are
restarts the
w h
eam is
d
Default
0
ee the
it
u