ADAU1781 Analog Devices, ADAU1781 Datasheet
ADAU1781
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ADAU1781 Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. Low Noise Stereo Codec with GENERAL DESCRIPTION The ADAU1781 is a low power, 24-bit stereo audio codec. The low noise DAC and ADC support sample rates from 8 kHz to 96 kHz. Low current draw and power saving modes make the ADAU1781 ideal for battery-powered audio applications. A programmable SigmaDSP® ...
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... ADAU1781 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Record Side Performance Specifications ................................... 4 Output Side Performance Specifications ................................... 6 Power Supply Specifications........................................................ 8 Typical Power Management Measurements ............................. 9 Digital Filters ................................................................................. 9 Digital Input/Output Specifications......................................... 10 Digital Timing Specifications ................................................... 11 Absolute Maximum Ratings .......................................................... 14 Thermal Resistance .................................................................... 14 ESD Caution ...
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... Changes to Figure 24 ...................................................................... 22 Changes to Figure 25 ...................................................................... 23 Changes to Table 33 ........................................................................ 48 Added Register 16434 (0x4032), Dejitter Control Section ........ 81 Changes to Ordering Guide ........................................................... 89 12/09—Revision 0: Initial Version Audio Converter Configuration ............................................... 63 Playback Path Configuration .................................................... 68 Pad Configuration ...................................................................... 75 Digital Subsystem Configuration ............................................. 82 Outline Dimensions ........................................................................ 89 Ordering Guide ........................................................................... 89 Rev Page ADAU1781 ...
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... ADAU1781 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C; master clock (MCLK) = 12.288 MHz ( kHz, 256 × word width = 24 bits; load capacitance (digital output pF; load current (digital output mA; high level input voltage = 0.7 × IOVDD; ...
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... AVDD = 3.3 V, 100 mV rms, 1 kHz AVDD = 3.3 V, 100 mV rms, 20 kHz Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V −3 dBFS input, measured at AOUTL pin, beep gain set AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Rev. B| Page ADAU1781 Min Typ Max 0 32 −98 50 0.25 −1 −98 −55 −55 AVDD/3.3 ...
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... ADAU1781 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Beep Input Mute Attenuation Offset Error Gain Error Interchannel Gain Mismatch Beep Input PGA Gain Range Beep Playback Mixer Gain Range Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × ...
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... AVDD = 3 capacitor = 10 μF AVDD = 3.3 V,100 mV p-p at 217 Hz AVDD = 3.3 V, 100 mV p kHz AVDD = 3.3 V Mute set by Register 0x401F, Bit output power O Scales linearly with AVDD AVDD = 1.8 V AVDD = 3.3 V Rev. B| Page ADAU1781 Min Typ Max 99 94 103 97 92 100 −88 −88 99 103 ...
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... ADAU1781 Parameter Total Harmonic Distortion + Noise Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, Beep to Mixer Path Muted REFERENCE (CM PIN) Common-Mode Reference Output POWER SUPPLY SPECIFICATIONS AVDD1 and AVDD2 must always be equal ...
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... Rev. B| Page kHz, analog and digital input tones are S Typical ADC Typical Line Output THD + N (dB) THD + N (dB) 88.5 93.0 88.5 93.0 88.5 93.0 88.5 93.0 88.0 87.5 88.0 87.5 88.0 87.5 88.0 87.5 88.5 94.5 88.5 94.5 88.5 94.5 88.5 94.5 89.0 90.5 89.0 90.5 89.0 90.5 89.0 90.5 88.5 89.5 88.5 89.5 88.5 89.5 88.5 89.5 86.5 85.5 86.5 85.5 86.5 85.5 86.5 85.5 88.5 90.5 88.5 90.5 88.5 90.5 88.5 90.5 88.0 88.0 88.0 88.0 88.0 88.0 88.0 88.0 Factor Min Typ 0.4375 × ±0.015 0.5 × 0.5625 × 22.9844/f 479 S ADAU1781 Max Unit kHz dB kHz kHz dB µs ...
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... ADAU1781 Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATIONS −25°C < T < +85°C, IOVDD = 1. 3.63 V, unless otherwise specified. A Table 6. Parameter HIGH LEVEL INPUT VOLTAGE ( LOW LEVEL INPUT VOLTAGE (V ...
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... Bus-free time. Time between stop and start MΩ Digital microphone clock fall time Digital microphone clock rise time Digital microphone delay time for valid data Digital microphone delay time for data three-stated. Rev. B| Page ADAU1781 = 14 pF. L ...
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... ADAU1781 Digital Timing Diagrams t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_SDATA MODE DAC_SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) t BIH BCLK t BIL LRCLK ...
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... Figure 4. SPI Port Timing SDR SDF t SCR SCLH SCS SCLL SCF 2 Figure Port Timing t t DCF DCR t t DDH DDH t DDV DATA2 DATA1 DATA2 Figure 6. Digital Microphone Timing Rev. B| Page ADAU1781 t CLH t CLPH t COD t SCH t BFT t DDV ...
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... ADAU1781 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Power Supply (AVDD1 = AVDD2) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... GPIO 7 SCL/CCLK 8 NOTES CONNECT. 2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1781 GROUNDS. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 7. 32-Lead LFCSP Pin Configuration 1 Description VDD/2 V Common-Mode Reference μ μF decoupling capacitor should be connected between this pin and ground to reduce crosstalk between the ADCs and DACs ...
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... Differential Source/Digital Microphone Input 1. Beep Signal Input. Microphone Bias. Exposed Pad. The exposed pad is connected internally to the ADAU1781 grounds. For increased reliability of the solder joints and maximum thermal capability recommended that the pad be soldered to the ground plane. Rev Page ...
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... S Figure Rev. B| Page 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 f FREQUENCY (NORMALIZED Normalized 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 f FREQUENCY (NORMALIZED Figure 12. ADC Decimation Filter, Double-Rate Mode, Normalized 0.05 0.10 0.15 0.20 0.25 0.30 f FREQUENCY (NORMALIZED ADC Decimation Filter Pass-Band Ripple, Double-Rate Mode, 13 Normalized ADAU1781 0.45 0.50 0.9 1.0 0.35 0.40 ...
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... ADAU1781 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 14. DAC Interpolation Filter, 64× Oversampling, Normalized 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0 0.05 0.10 0.15 0.20 0.25 FREQUENCY (NORMALIZED TO Figure 15. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling, Normalized –10 –20 – ...
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... SPEAKER OUTPUT POWER (mW) Figure 20. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply 0 –20 –40 –60 –80 –100 100 600 Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 1.8 V Supply Rev. B| Page ADAU1781 1 10 100 SPEAKER OUTPUT POWER (mW) ...
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... PDN PDN IOVDD AVDD1 10µF 10µF 10µF AVDD2 47µF 0.1µF 0.1µF 0.1µF 0.1µF SPN SPP AOUTL AOUTR ADAU1781 CM 100nF GPIO DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK Figure 22. System Block Diagram with Differential Inputs Rev Page – 8Ω SPEAKER ...
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... SPN SPP AOUTL AOUTR ADAU1781 CM 100nF GPIO DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK Rev. B| Page ADAU1781 – 8Ω SPEAKER + OUT 100pF STEREO SINGLE-ENDED HEADPHONE OUTPUT 10kΩ 10kΩ LEFT_OUT 10Ω 220µF CM 10kΩ 100pF 10kΩ ...
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... IOVDD AVDD1 10µF 10µF 10µF AVDD2 47µF 0.1µF 0.1µF 0.1µF 0.1µF SPN SPP AOUTL LMIC/LMICN/MICD1 AOUTR LMICP ADAU1781 RMIC/RMICN/MICD2 RMICP CM GPIO BEEP DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 BCLK/GPIO2 LRCLK/GPIO3 MCKI ADDR1/CLATCH ADDR0/CDATA SDA/COUT SCL/CCLK MCKO PDN Figure 24. System Block Diagram with Single-Ended Stereo Line Inputs Rev Page – ...
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... GPIO DAC_SDATA/GPIO0 ADC_SDATA/GPIO1 SERIAL DATA BCLK/GPIO2 LRCLK/GPIO3 ADDR1/CLATCH ADDR0/CDATA SYSTEM CONTROLLER SDA/COUT SCL/CCLK Rev. B| Page ADAU1781 8Ω SPEAKER OUT 100pF STEREO SINGLE-ENDED HEADPHONE OUTPUT 10kΩ LEFT_OUT 10Ω 220µF 10kΩ 100pF 10kΩ 10kΩ 10Ω 220µF ...
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... The ADAU1781 can generate its internal clocks from a wide range of input clocks by using the on-board fractional PLL. The PLL accepts inputs from 11 MHz to 20 MHz. The ADAU1781 is provided in a small, 32-lead × lead frame chip scale package (LFCSP) with an exposed bottom pad. Rev Page ...
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... The POR monitors the DVDDOUT pin and generates a reset signal whenever power is applied to SUPPLY POWER TO AVDD1 the chip. During the reset, the ADAU1781 is set to the default values documented in the register map (see the Control Register SUPPLY POWER TO AVDD2 Map section) ...
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... For more information, see the DSP Core section POWER REDUCTION MODES Sections of the ADAU1781 chip can be turned on and off as needed to reduce power consumption. These include the ADCs, the DACs, and the PLL. In addition, some functions can be set in the registers to operate in power saving, normal, or enhanced performance operation. ...
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... Bit Name Settings Clock source select 0: direct from MCKI pin (default) 1: PLL clock Input master clock 00: 256 × f (default) S frequency 01: 512 × 10: 768 × 11: 1024 × Core clock enable 0: core clock disabled (default) 1: core clock enabled ADAU1781 DACs ...
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... ADAU1781 Table 14 and Table 15 list the sampling rate divisions for common base sampling rates. Table 14. Base Sampling Rate Divisions for f Base Sampling Frequency Sampling Rate Scaling kHz /1 /0.5 S Table 15. Base Sampling Rate Divisions for f ...
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... Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock Core Clock Sampling Rate Divider 11.2896 MHz (1 × 256) (6 × 256) (4 × 256) (3 × 256) (2 × 256) (1.5 × 256) (0.5 × 256) Rev. B| Page ADAU1781 Sampling Rate 48 kHz 8 kHz 12 kHz 16 kHz 24 kHz 32 kHz 96 kHz Sampling Rate 44.1 kHz 7.35 kHz 11 ...
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... ADC CM Figure 30. Record Signal Path Diagram INPUT SIGNAL PATH The ADAU1781 can be configured for three types of microphone inputs: single-ended, differential, or digital. The LMIC/LMICN/ MICD1 and RMIC/RMICN/MICD2 pins encompass all of these configurations. LMICP and RMICP are used only during differen- tial configurations (see Figure 30, the record signal path diagram). ...
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... ANALOG-TO-DIGITAL CONVERTERS The ADAU1781 uses two 24-bit Σ-Δ analog-to-digital converters (ADCs) with selectable oversampling rates of either 64× or 128×. The full-scale input to the ADCs depends on AVDD1. At 3.3 V, the full-scale input level is 1.0 V rms. Inputs greater than the full-scale value result in clipping and distortion. ...
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... MIXER Figure 34. Playback Signal Path Diagram OUTPUT SIGNAL PATHS The outputs of the ADAU1781 include a left and right line output and speaker driver. The beep input signal can be mixed into any of these outputs, with separate gain control for each path. DIGITAL-TO-ANALOG CONVERTERS The ADAU1781 uses two 24-bit Σ ...
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... ADAU1781 and the system mode, the ADAU1781 is always a slave on the bus, meaning it cannot initiate a data transfer. Each slave device is recognized by a unique address. The address byte format is shown in Table 21. The address resides in the first seven bits of the I LSB of this byte sets either a read or write operation ...
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... SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register acknowledge is issued by the ADAU1781, and the part returns to the idle condition. R/W ...
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... Figure 40 shows the timing of a burst mode write sequence. This figure shows an example where the target destination registers are two bytes. The ADAU1781 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2-byte word length ...
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... All SPI transactions have the same basic format shown in Table 24. A timing diagram is shown in Figure 4. All data should be written MSB first. The ADAU1781 can be taken out of SPI mode only by a full reset. W Chip Address R/ The first byte of an SPI transaction includes the 7-bit chip address and bit ...
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... CLATCH CCLK CDATA BYTE 0 Figure 43. SPI Write to ADAU1781 Clocking (Single-Write Mode) CLATCH CCLK CDATA BYTE 0 HIGH-Z COUT Figure 44. SPI Read from ADAU1781 Clocking (Single-Read Mode) BYTE 1 BYTE 1 BYTE 3 DATA Rev. B| Page ADAU1781 BYTE 2 BYTE 3 HIGH-Z DATA ...
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... The ADAU1781 TDM implementation is a TDM audio stream. Unlike a true TDM bus, its output does not become high imped- ance during periods when it is not transmitting data. In TDM 8 mode, the ADAU1781 can be a master for f 48 kHz. Table 25 lists the modes in which the serial output port can function. ...
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... LRCLK BCLK MSB MSB – 1 MSB – 2 DATA Figure 49. TDM Mode SLOT 2 SLOT 3 SLOT 4 SLOT 5 Figure 50. TDM Mode with Pulse Word Clock Rev. B| Page ADAU1781 LSB RIGHT CHANNEL LSB RIGHT CHANNEL MSB LSB SLOT 7 SLOT 8 MSB TDM 8TH CH SLOT 6 SLOT 7 ...
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... ADAU1781 GENERAL-PURPOSE INPUT/OUTPUTS The serial data input/output pins are shared with the general- purpose input/output function. Each of these four pins can be set to only one function. The function of these pins is set in Register 16628 (0x40F4), serial data/GPIO pin configuration. The GPIO pins can be used as either inputs or outputs. These pins are readable and can be set either through the control interface or directly by the SigmaDSP core ...
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... DSP CORE SIGNAL PROCESSING The ADAU1781 is designed to provide all audio signal processing functions commonly used in stereo or mono low power record and playback systems. The signal processing flow is designed using the SigmaStudio™ software, which allows graphical entry and real-time control of all signal processing functions. ...
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... Figure 52. Numeric Precision and Clipping Structure PROGRAMMING On power-up, the ADAU1781 must be set with a clocking scheme and then loaded with register settings. After the codec signal path is set up, the DSP core can be programmed. There are 1024 instruction cycles per audio sample, resulting in an internal clock rate of 49 ...
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... Figure 53. SigmaStudio Screen Shot Rev. B| Page ADAU1781 ...
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... SigmaStudio automatically assigns the first eight positions to safeload parameters; therefore, project-specific parameters start at Address 0x0008. DATA RAM The ADAU1781 data RAM is used to store audio data-words for processing. The user cannot directly address this RAM space, which has a size of 512 words, from the control port. Address Range ...
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... PROG_ADR[15:8] SOFTWARE SAFELOAD To update parameters in real time while avoiding pop and click noises on the output, the ADAU1781 uses a software safeload mechanism. The software safeload mechanism enables the SigmaDSP core to load new parameters into RAM while guaranteeing that the parameters are not in use. This prevents an undesirable condition where an instruction may execute with a mix of old and new parameters ...
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... ADAU1781 SOFTWARE SLEW When the values of signal processing parameters are changed abruptly in real time, they sometimes cause pop and click sounds to appear on the audio outputs. To avoid pops and clicks, some algorithms in SigmaStudio implement a software slew functionality. Algorithms using software slew set a target value for a parameter and continuously update the value of that parameter until it reaches the target ...
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... AVDD1 pin (up to 300 mA). An appro- priately thick trace is recommended. EXPOSED PAD PCB DESIGN The ADAU1781 LFCSP package has an exposed pad on the underside. This pad is used to couple the package to the PCB for heat dissipation when using the outputs to drive earpiece or headphone loads ...
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... ADAU1781 CONTROL REGISTER MAP All registers except the PLL control register are 1-byte write and read registers. Table 33. Address Hex Decimal 0x4000 16384 0x4001 16385 0x4002 16386 0x4008 16392 0x4009 16393 0x400E 16398 0x400F 16399 0x4010 16400 0x4015 16405 0x4016 16406 ...
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... Register 16384 (0x4000), Clock Control The clock control register sets the clocking scheme for the ADAU1781. The system clock can be generated from either the PLL or directly from the MCKI (master clock input) pin. Addi- tionally, the MCKO (master clock output) pin can be configured. ...
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... ADAU1781 Register 16385 (0x4001), Regulator Control Bits[2:1], Regulator Output Level These bits set the regulated voltage output for the digital core, DVDDOUT. After the initialization sequence has completed, the regulator output is set to 1.4 V. The recommended regulator output level when the device begins to process audio is 1.5 V. ...
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... Input divider 00: no division 01: divide 10: divide 11: divide PLL type 0: integer-N 1: fractional [7:2] Reserved 1 PLL lock (read only) 0: unlocked 1: locked (sticky bit) 0 PLL enable 0: disabled 1: enabled Rev. B| Page ADAU1781 Default 00000111 01010011 00000010 10000111 0011 ...
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... ADAU1781 Table 39. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 1 19.2 1 19.68 1 19.8 1 Table 40. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 1 19.2 1 19. 44.1 kHz (f = 44.1 kHz, Core Clock = 256 × 44.1 kHz, PLL Clock = 45.1584 MHz) ...
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... Bits[2:0], Beep Input Gain This bit controls the gain setting for the analog beep input; it defaults and can be set as high as 32 dB. The beep signal must be enabled in Register 16400 (0x4010), microphone bias control and beep enable. Rev. B| Page ADAU1781 Default 00 0 000 ...
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... ADAU1781 Register 16393 (0x4009), Record Power Management This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADC, front-end mixer, and PGAs can be set in one of four modes. The four modes of operation available that affect the performance of the device are normal operation, power saving, enhanced performance, and extreme power saving ...
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... PGA is switched to common mode. Bit 1, Record Path Left Mute This bit mutes the left channel input PGA. Bit 0, Left PGA Enable This bit enables the left channel input PGA Rev. B| Page ADAU1781 Default 000 ...
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... ADAU1781 Register 16399 (0x400F), Record Gain Right PGA The record gain right PGA control register controls the right channel input PGA. This register configures the input for either differential or single-ended signals and sets the right channel input recording volume. Bits[7:5], Right Input Gain These bits set the right channel analog microphone input PGA gain ...
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... Provides two voltage bias options, 0.65 × AVDD1 and 0.90 × AVDD1. A higher bias contributes to a higher microphone gain. The maximum current that can be drawn from MICBIAS is 5 mA. Bit 0, Microphone Bias Enable This bit enables the MICBIAS output. Rev. B| Page ADAU1781 Default ...
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... ADAU1781 SERIAL PORT CONFIGURATION Register 16405 (0x4015), Serial Port Control 0 Bit 5, LRCLK Mode This bit sets the serial port frame clock (LRCLK) as either a 50% duty cycle waveform or a pulse synchronization waveform. When in slave mode, the pulse should be at least 1 BCLK cycle wide to guarantee proper data transfer ...
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... Figure 59. Serial Port BCLK Polarity Figure 60. Serial Port LRCLK Polarity f 1/ LRCLK Figure 61. Channels per Frame f 1/ LRCLK SECOND PAIR 2 3 SECOND PAIR THIRD PAIR Figure 62. TDM Channel Pairs Rev. B| Page ADAU1781 FOURTH PAIR 7 8 ...
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... ADAU1781 Register 16406 (0x4016), Serial Port Control 1 Bits[7:5], Number of Bit Clock Cycles per Frame These bits set the number of BCLK cycles contained in one LRCLK period. The frequency of BCLK is calculated as the number of bit clock cycles per frame times the sample rate of the serial port in hertz. Figure 63 and Figure 64 show examples of different settings for these bits ...
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... Figure 67. MSB Position Settings Rev. B| Page SECOND PAIR LEFT RIGHT THIRD PAIR FOURTH PAIR RIGHT LEFT RIGHT SECOND PAIR RIGHT LEFT THIRD PAIR FOURTH PAIR LEFT RIGHT LEFT ADAU1781 ...
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... ADAU1781 LRCLK BCLK SERIAL DATA M (DELAY BY 0) SERIAL DATA M (DELAY BY 1) SERIAL DATA M (DELAY BY 8) LRCLK BCLK SERIAL DATA (DELAY BY 16 LRCLK ...
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... The higher rate yields slightly better audio quality but increases power consumption. Bits[2:0], Converter Sampling Rate These bits set the sampling rate of the audio ADCs and DACs relative to the SigmaDSP core’s audio sample rate. Rev. B| Page ADAU1781 Default 000 ...
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... ADAU1781 LRCLK TDM 4 CHANNELS FIRST PAIR LEFT TDM 8 CHANNELS LRCLK TDM 4 CHANNELS FIRST PAIR TDM 8 CHANNELS LRCLK FIRST PAIR TDM 8 CHANNELS f 1/ LRCLK FIRST PAIR LEFT RIGHT SECOND PAIR RIGHT Figure 70. Example of Left Channel First, First Pair TDM Setting f 1/ LRCLK ...
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... Register 16406 (0x4016), Serial Port Control 1, Bit 4, ADC channel position in TDM, to select where the data should appear in the TDM stream. Figure 70, Figure 71, and Figure 72 show examples of different TDM settings. Rev. B| Page ADAU1781 Default 00 ...
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... This bit must be configured accordingly to recognize a valid output state of the microphone. The default is negative, meaning that a digital logic low signal is recognized by the ADAU1781 as a pulse in the PDM signal. Table 50. ADC Control Register ...
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... When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process. The slew ramp is logarithmic, incrementing 0.375 dB per audio frame. Rev. B| Page ADAU1781 Default 00000000 Default 00000000 ...
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... ADAU1781 PLAYBACK PATH CONFIGURATION Register 16412 (0x401C), Playback Mixer Left Control Bit 5, Left DAC Mute This bit mutes the left DAC output. It does not have any slew and is updated immediately when the register write has been completed. This results in an abrupt cutoff of the audio output and should therefore be preceded by a soft mute in the SigmaDSP core or a slew mute using the DAC attenuator ...
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... Bit 0, Clamp Amplifier Control This bit enables or disables the clamp amp enabled by default. The clamp amp should usually be enabled in systems where the line outputs are used. Rev. B| Page ADAU1781 Default 0 0 0000 0 ...
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... ADAU1781 Register 16421 (0x4025), Left Line Output Mute Bit 1, Left Line Output Mute This bit mutes the left line output. It does not have any effect on the speaker outputs. Table 57. Left Line Output Mute Register Bits Description [7:2] Reserved 1 Left line output mute (active low) ...
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... Bit 0, Zero-Crossing Detector Enable This bit enables the zero-crossing detector. Disabling the beep zero-crossing detector may cause clicks and pops on the output when using the beep path. Rev. B| Page ADAU1781 Default 00 0 Default 11 ...
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... ADAU1781 Register 16425 (0x4029), Playback Power Management This register controls the unity current supplied to each functional block described. Within the functional blocks, the current can be multiplied. Normal operation has a base current of 2.5 μA, enhanced performance has a base current of 3 μA, power saving has a base current of 2 μ ...
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... This bit enables a de-emphasis filter and should be used when a preemphasized signal is input to the DACs. Bits[1:0], DAC Enable These bits allow the DACs to be individually enabled or disabled. Disabling unused DACs can result in significant power savings. Rev. B| Page ADAU1781 Default ...
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... ADAU1781 Register 16427 (0x402B), Left DAC Attenuator Bits[7:0], Left DAC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, the volume control slews gradually to the new value, avoiding pops and clicks in the process ...
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... DATA OUT LEVEL SHIFTER INPUT ENABLE PULL-UP ENABLE LEVEL SHIFTER PULL-DOWN ENABLE WEAK PULL-UP/PULL-DOWN 190kΩ WORST CASE LEVEL SHIFTER Figure 73. Pad Configuration, Internal Design Rev. B| Page OUTPUT CONTROL LOGIC INPUT ESD 240kΩ NOMINAL ADAU1781 6× PAD 12× ...
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... ADAU1781 Register 16429 (0x402D), Serial Port Pad Control 0 Bits[7:6], ADC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], DAC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ ...
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... High mode yields 4 mA when IOVDD = 3 1.5 mA when IOVDD = 1.8 V. Bit 0, BCLK Pin Drive Strength This bit sets the drive strength of the BCLK pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3 1.5 mA when IOVDD = 1.8 V. Rev. B| Page ADAU1781 Default ...
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... ADAU1781 Register 16431 (0x402F), Communication Port Pad Control 0 Bits[7:6], CDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], CLATCH Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ ...
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... Bit 0, SDA/COUT Pin Drive Strength This bit sets the drive strength of the SDA/COUT pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3 1.5 mA pin. Low mode when IOVDD = 1.8 V. Rev. B| Page ADAU1781 Default ...
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... ADAU1781 Register 16433 (0x4031), MCKO Control Bit 2, MCKO Pin Drive Strength This bit sets the drive strength of the MCKO pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = 1.8 V. High mode yields 4 mA when IOVDD = 3 1.5 mA when IOVDD = 1.8 V. Table 69. MCKO Control Register ...
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... ADCs, serial port, sound engine/DSP core, or DACs, the dejitter circuit can be bypassed and reset by setting the dejitter window size to 0. Then, the dejitter circuit can be immediately reactivated, without a wait period, by setting the dejitter window size to the default value of 5. Rev. B| Page ADAU1781 Default 00000101 ...
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... Setting this bit to 0 disables the internal clock generator, which generates all master clocks for the serial ports, SigmaDSP core, ADCs, and DACs. This bit must be enabled if audio is being passed through the ADAU1781. Bit 0, SigmaDSP Core Setting this bit to 0 disables the SigmaDSP core and makes the memory inaccessible ...
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... Zero-crossing detector 0: disabled 1: enabled 1 Digital microphone 0: disabled 1: enabled 0 DAC engine 0: disabled 1: enabled Bit 1, Digital Microphone Setting this bit to 0 disables the digital microphone input. Bit 0, DAC Engine Setting this bit to 0 disables the DACs. Rev. B| Page ADAU1781 Default ...
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... ADAU1781 Register 16582 to Register 16586 (0x40C6 to 0x40CA), GPIO Pin Control Bits[3:0], GPIO Pin Function The GPIO pin control register sets the functionality of each GPIO pin as depicted in Table 74. GPIO0 to GPIO3 use the same pins as the serial port and must be enabled in Register 16628 (0x40F4), serial data/GPIO pin configuration ...
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... It effectively determines the sample rate of audio in the SigmaDSP core. This register should always be set to none at least one frame prior to disabling Register 16630 (0x40F6), SigmaDSP core run, Bit 0, SigmaDSP core run, to allow the SigmaDSP core to finish processing the current frame before halting. Rev. B| Page ADAU1781 Default 0000 ...
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... ADAU1781 Register 16626 (0x40F2), Serial Input Route Control Bits[3:0], Input Routing These bits select which serial data input channels are routed to the DACs (see Figure 74). Table 78. Serial Input Route Control Register Bits Description [7:4] Reserved [3:0] Input routing 0000: serial input to SigmaDSP core to DACs ...
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... ADCs [ serial output [R3, L3 left side of Channel right side of Channel x. LRCLK STEREO CHANNELS TDM 4 CHANNELS L0 TDM 8 CHANNELS LRCLK Figure 74. Serial Port Routing Control Rev. B| Page ADAU1781 Default 0000 ...
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... ADAU1781 Register 16628 (0x40F4), Serial Data/GPIO Pin Configuration Bits[3:0], GPIO[0:3] The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, then the GPIO[0:3] pins become GPIO interfaces to the SigmaDSP core. If these bits are set to 0, they remain LRCLK, BCLK, or serial port data pins, respectively ...
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... LFCSP_VQ, 7” Tape and Reel Evaluation Board Rev. B| Page 0.60 MAX PIN 1 INDICATOR EXPOSED 3.65 PAD 3.50 SQ (BOTTOM VIEW) 3. 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-32-4 CP-32-4 ADAU1781 ...
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... ADAU1781 NOTES Rev Page ...
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... NOTES Rev. B| Page ADAU1781 ...
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... ADAU1781 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...