LPC11U13FBD48 NXP Semiconductors, LPC11U13FBD48 Datasheet - Page 19

• Manufacturer Part Number: LPC11U13FBD48
• Description: The LPC11U13FBD48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11U1X
Product data sheet
7.8.1.1 Features
7.7.1 Features
7.8.1 Full-speed USB device controller
7.8 USB interface
7.9 USART
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC11U1x USB interface consists of a full-speed device controller with on-chip PHY
for device functions.
Remark: Configure the LPC11U1x in default power mode with the power profiles before
using the USB (see
efficiency, or low-power mode.
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
The LPC11U1x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
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GPIO pins can be configured as input or output by software.
All GPIO pins default to inputs with interrupt disabled at reset.
Pin registers allow pins to be sensed and set individually.
Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
Port interrupts can be triggered by any pin or pins in each port.
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 10 physical (5 logical) endpoints including one control endpoint.
Single and double buffering supported.
Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
Supports wake-up from Deep-sleep mode and Power-down mode on USB activity
and remote wake-up.
Supports SoftConnect.
All information provided in this document is subject to legal disclaimers.
Section
Rev. 2 — 11 January 2012
7.16.5.1). Do not use the USB with the part in performance,
32-bit ARM Cortex-M0 microcontroller
LPC11U1x
© NXP B.V. 2012. All rights reserved.
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