LPC11U13FBD48 NXP Semiconductors, LPC11U13FBD48 Datasheet - Page 49

• Manufacturer Part Number: LPC11U13FBD48
• Description: The LPC11U13FBD48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 16.
[1]
[2]
LPC11U1X
Product data sheet
[3]
[4]
Symbol
SPI master (in SPI mode)
T
t
t
t
t
SPI slave (in SPI mode)
T
t
t
t
t
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
cy(clk)
cy(PCLK)
T
main clock frequency f
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
= 40 C to 85 C.
= 25 C; for normal voltage supply range: V
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
= 12  T
Dynamic characteristics of SPI pins in SPI mode
Parameter
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
PCLK cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
10.6 SSP interface
cy(PCLK)
main
.
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
Conditions
full-duplex mode
when only transmitting
in SPI mode
in SPI mode
in SPI mode
in SPI mode
2.4 V  V
2.0 V  V
1.8 V  V
All information provided in this document is subject to legal disclaimers.
DD
DD
DD
DD
 3.6 V
< 2.4 V
< 2.0 V
Rev. 2 — 11 January 2012
main
= 3.3 V.
. The clock cycle time derived from the SPI bit rate T
[1]
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[3][4]
[3][4]
[3][4]
[3][4]
Min
50
40
15
20
24
0
-
0
20
0
3  T
-
-
cy(PCLK)
32-bit ARM Cortex-M0 microcontroller
+ 4
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
10
-
-
-
-
3  T
2  T
cy(PCLK)
cy(PCLK)
LPC11U1x
cy(clk)
© NXP B.V. 2012. All rights reserved.
is a function of the
+ 11
+ 5
49 of 69
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns