LPC11U13FBD48 NXP Semiconductors, LPC11U13FBD48 Datasheet - Page 27

• Manufacturer Part Number: LPC11U13FBD48
• Description: The LPC11U13FBD48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11U1X
Product data sheet
7.16.5.5 Deep power-down mode
7.16.6.1 Reset
7.16.6.2 Brownout detection
7.16.6.3 Code security (Code Read Protection - CRP)
7.16.6 System control
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC11U1x can wake up from Deep power-down mode via the
WAKEUP pin.
The LPC11U1x can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU block. Locking out Deep power-down mode enables the user to always
keep the watchdog timer or the BOD running.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
Reset has four sources on the LPC11U1x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
The LPC11U1x includes four levels for monitoring the voltage on the V
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
This feature of the LPC11U1x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC11U1x user manual.
There are three levels of Code Read Protection:
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 January 2012
32-bit ARM Cortex-M0 microcontroller
LPC11U1x
DD
© NXP B.V. 2012. All rights reserved.
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