LPC11U13FBD48 NXP Semiconductors, LPC11U13FBD48 Datasheet - Page 26

The LPC11U13FBD48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/

LPC11U13FBD48

Manufacturer Part Number
LPC11U13FBD48
Description
The LPC11U13FBD48 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC11U13FBD48/201
Manufacturer:
NXP
Quantity:
1 000
Company:
Part Number:
LPC11U13FBD48/201
Quantity:
10
Part Number:
LPC11U13FBD48/201,
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC11U1X
Product data sheet
7.16.5.1 Power profiles
7.16.5.2 Sleep mode
7.16.5.3 Deep-sleep mode
7.16.5.4 Power-down mode
on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic
power use in any peripherals that are not required for the application. Selected
peripherals have their own clock divider which provides even better power control.
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11U1x for one of the following power modes:
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
Remark: When using the USB, configure the LPC11U1x in Default mode.
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
In Deep-sleep mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all
clock sources are off with the exception of the IRC. The IRC output is disabled unless the
IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down
and the flash is in stand-by mode. In Deep-sleep mode, the user has the option to keep
the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD
protection.
The LPC11U1x can wake up from Deep-sleep mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
Deep-sleep mode saves power and allows for short wake-up times.
In Power-down mode, the LPC11U1x is in Sleep-mode and all peripheral clocks and all
clock sources are off with the exception of watchdog oscillator if selected. In addition all
analog blocks and the flash are shut down. In Power-down mode, the user has the option
to keep the BOD circuit running for BOD protection.
The LPC11U1x can wake up from Power-down mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
Default mode corresponding to power configuration after reset.
CPU performance mode corresponding to optimized processing capability.
Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 January 2012
32-bit ARM Cortex-M0 microcontroller
LPC11U1x
© NXP B.V. 2012. All rights reserved.
26 of 69

Related parts for LPC11U13FBD48