LPC11U14FHI33 NXP Semiconductors, LPC11U14FHI33 Datasheet - Page 16
![The LPC11U14FHI33 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/](/photos/41/52/415286/sot617-3_3d_sml.gif)
LPC11U14FHI33
Manufacturer Part Number
LPC11U14FHI33
Description
The LPC11U14FHI33 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
Manufacturer
NXP Semiconductors
Datasheet
1.LPC11U12FBD48.pdf
(69 pages)
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NXP Semiconductors
7. Functional description
LPC11U1X
Product data sheet
7.1 On-chip flash programming memory
7.2 SRAM
7.3 On-chip ROM
7.4 Memory map
The LPC11U1x contain up to 32 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
The LPC11U1x contain a total of 6 kB on-chip static RAM memory.
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
The LPC11U1x incorporates several distinct memory regions, shown in the following
figures.
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
•
•
•
In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
Power profiles for configuring power consumption and PLL settings
32-bit integer division routines
Figure 5
All information provided in this document is subject to legal disclaimers.
shows the overall map of the entire address space from the user
Rev. 2 — 11 January 2012
32-bit ARM Cortex-M0 microcontroller
LPC11U1x
© NXP B.V. 2012. All rights reserved.
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