LPC11U14FHI33 NXP Semiconductors, LPC11U14FHI33 Datasheet - Page 28

• Manufacturer Part Number: LPC11U14FHI33
• Description: The LPC11U14FHI33 is a ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11U1X
Product data sheet
CAUTION
7.16.6.4 APB interface
7.16.6.5 AHBLite
7.16.6.6 External interrupt inputs
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11U1x user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
All GPIO pins can be level or edge sensitive interrupt inputs.
1. CRP1 disables access to the chip via the SWD and allows partial flash update
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to the chip
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 January 2012
32-bit ARM Cortex-M0 microcontroller
LPC11U1x
© NXP B.V. 2012. All rights reserved.
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