LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 107
LPC1820FET100
Manufacturer Part Number
LPC1820FET100
Description
The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1810FBD144.pdf
(157 pages)
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NXP Semiconductors
LPC1850_30_20_10
Preliminary data sheet
11.6 I
Table 14.
T
refer to I2S0 and I2S1 pins. Simulated values.
[1]
2
Symbol
common to input and output
t
t
t
t
output
t
input
t
t
amb
Fig 25. I
r
f
WH
WL
v(Q)
su(D)
h(D)
S-bus interface
I2Sx_TX_SCK
I2Sx_TX_SDA
I2Sx_TX_WS
Clock to the I
PCLK = BASE_APB1_CLK / 12. I
I
2
= 25
S-bus specification.
2
C; 2.2 V
Dynamic characteristics: I
S-bus timing (transmit)
Parameter
rise time
fall time
pulse width HIGH
pulse width LOW
data output valid time on pin I2Sx_TX_SDA
data input set-up time on pin I2Sx_RX_SDA
data input hold time
2
S-bus interface BASE_APB1_CLK = 150 MHz; peripheral clock to the I
All information provided in this document is subject to legal disclaimers.
V
Rev. 3.1 — 15 December 2011
DD(REG)(3V3)
t
WH
2
S clock cycle time T
Conditions
on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
on pins I2Sx_TX_SCK
and I2Sx_RX_SCK
on pin I2Sx_TX_WS
on pin I2Sx_RX_WS
on pin I2Sx_RX_SDA
on pin I2Sx_RX_WS
T
3.6 V; 2.7 V
cy(clk)
2
t
S-bus interface pins
v(Q)
t
v(Q)
t
WL
V
cy(clk)
DD(IO)
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
= 79.2 ns; corresponds to the SCK signal in the
[1]
[1]
[1]
3.6 V; C
Min
-
-
<tbd>
-
-
-
-
-
-
L
= 20 pF. Conditions and data
t
f
Typ
4
4
-
-
4.4
4.3
0
0.20
3.7
3.9
© NXP B.V. 2011. All rights reserved.
2
S-bus interface
Max
-
-
<tbd>
-
-
-
-
-
-
t
r
002aag497
107 of 157
Unit
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
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