LPC1820FET100 NXP Semiconductors, LPC1820FET100 Datasheet - Page 151

The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2

LPC1820FET100

Manufacturer Part Number
LPC1820FET100
Description
The LPC1820FET100 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 168 kB of SRAM, and advanced peripherals including High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet

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LPC1820FET100
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NXP Semiconductors
Table 35.
LPC1850_30_20_10
Preliminary data sheet
Document ID
Modifications:
LPC1850_30_20_10 v.2.2
Modifications:
LPC1850_30_20_10 v.2.1
Modifications:
Revision history
…continued
Release date Data sheet status
20110909
20110822
Updates related to the Rev ‘A’ version of parts LPC1850/30/20/10:
– LQFP208 pin configuration added.
– SRAM connections in Figure 8 updated and SPIFI added.
– EMC static and dynamic SRAM characterization data added.
– Number of GPIOs corrected in the LQFP208 package (Table 2).
– Table 8 updated for parts LPC1850/30/20/10 Rev ‘A’.
– ADC characteristics added (Table 25.
– DAC characteristics added (Table 26).
– Reset state updated for pin PF_0 and PF_4 in Table 3.
– Power consumption data added in Table 8.
– Pin electrical characteristics added in Table 8, Figure 20 and Figure 21.
Pin P7_2, column LQFP144: replaced 113 by 115 in Table 3.
LQFP100 pin package added in Table 3.
Number of ADC channels, QEI, and Motor control PWM added in Table 2.
Pin P2_7 designated as ISP entry pin.
Description of ISP mode added (see Section 7.8.1).
Updates related to the Rev ‘A’ version of parts LPC1850/30/20/10:
– V
– Boot pins corrected in Table 3 and Table 5: Pin P2_7 replaced by pin P2_9 as boot
– USART3 boot mode added in Table 5.
– Memory map updated: SPIFI data added at address 0x1400 000 in Figure 9.
– Boot ROM size increased to 64 kB in Section 2 and Figure 9.
Updated pin P2_2, CTOUT_6 changed to CTIN_6 in Table 3.
pin. Pin level corrected for 4th boot pin (P2_9) in Table 5.
All information provided in this document is subject to legal disclaimers.
I
updated for I/O pins in Table 6.
Rev. 3.1 — 15 December 2011
Preliminary data sheet
Preliminary data sheet
Change notice Supersedes
-
-
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
LPC1850_30_20_10 v.2.1
LPC1850_30_20_10 v.2
© NXP B.V. 2011. All rights reserved.
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