LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 21

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
6.8.2 Pin description
6.8.3 Clock description
6.8.4 Flash layout
When an AHB data port read transfer requires data from a different flash word to that
involved in the previous read transfer, a new flash read is done and wait states are given
until the new read data is available.
With dual buffering, a secondary buffer line is used, the output of the flash being
considered as the primary buffer. On a primary buffer, hit data can be copied to the
secondary buffer line, which allows the flash to start a speculative read of the next flash
word.
Both buffer lines are invalidated after:
The modes of operation are listed in
Table 9.
The flash memory controller has no external pins. However, the flash can be programmed
via the JTAG pins, see
The flash memory controller is clocked by CLK_SYS_FMC, see
The ARM processor can program the flash for ISP (In-System Programming) through the
flash memory controller. Note that the flash always has to be programmed by ‘flash words’
of 128 bits (four 32-bit AHB bus words, hence 16 bytes).
The flash memory is organized into eight ‘small’ sectors of 8 kB each and up to 11 ‘large’
sectors of 64 kB each. The number of large sectors depends on the device type. A sector
must be erased before data can be written to it. The flash memory also has sector-wise
protection. Writing occurs per page which consists of 4096 bits (32 flash words). A small
sector contains 16 pages; a large sector contains 128 pages.
Synchronous timing
No buffer line
Single buffer line
Asynchronous timing
No buffer line
Single buffer line
Dual buffer line, single
speculative
Dual buffer line, always
speculative
•
•
•
•
Initialization
Configuration-register access
Data-latch reading
Index-sector reading
Flash read modes
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
Section
for single (non-linear) reads; one flash-word read per word read
default mode of operation; most recently read flash word is kept until
another flash word is required
one flash-word read per word read
most recently read flash word is kept until another flash word is
required
on a buffer miss a flash read is done, followed by at most one
speculative read; optimized for execution of code with small loops
(less than eight words) from flash
most recently used flash word is copied into second buffer line; next
flash-word read is started; highest performance for linear reads
6.6.3.
Table
ARM9 microcontroller with CAN, LIN, and USB
9.
LPC2926/2927/2929
Section
© NXP B.V. 2010. All rights reserved.
6.7.2.
21 of 95