LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 27

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
6.10.2 Clock description
6.11.1 USB device controller
6.11.2 USB OTG controller
6.11 USB interface
The GPDMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see
Section
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic
configuration of the devices. All transactions are initiated by the Host controller.
The LPC2926/2927/2929 USB interface includes a device and OTG controller with
on-chip PHY for device. The OTG switching protocol is supported through the use of an
external controller. Details on typical USB interfacing solutions can be found in
Section
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the on-chip
SRAM.
The USB device controller has the following features:
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals.
The OTG Controller integrates the device controller, and a master-only I
implement OTG dual-role device functionality. The dedicated I
external OTG transceiver.
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Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 2 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, the LPC2926/2927/2929 can enter the
Power-down mode and wake up on USB activity.
Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints.
Allows dynamic switching between CPU-controlled slave and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
6.7.2.
10.2.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
ARM9 microcontroller with CAN, LIN, and USB
LPC2926/2927/2929
2
C interface controls an
© NXP B.V. 2010. All rights reserved.
2
C interface to
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