LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 55

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
Fig 15. Block diagram of the CGU1
BASE_ICLK0_CLK
BASE_ICLK1_CLK
6.16.3.1 Pin description
6.16.3 Clock generation for USB (CGU1)
6.16.4 Reset Generation Unit (RGU)
The CGU1 block is functionally identical to the CGU0 block and generates two clocks for
the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and
fractional divider. The PLLs used in CGU0 and CGU1 are identical (see
The clock input to the CGU1 PLL is provided by one of two base clocks generated in the
CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK. The base clock not used for the PLL
can be configured to drive the output clock directly.
The CGU1 module in the LPC2926/2927/2929 has the pins listed in
Table 29.
The RGU controls all internal resets.
The key features of the Reset Generation Unit (RGU) are:
Symbol
CLK_OUT
•
PLL
CLOCK GENERATION UNIT
Reset controlled individually per subsystem
clkout
clkout120
clkout240
(CGU1)
CGU1 pins
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
Direction
OUT
AHB TO DTL BRIDGE
FDIV0
Description
clock output
ARM9 microcontroller with CAN, LIN, and USB
LPC2926/2927/2929
OUT 0
OUT 1
OUT 2
Table 28
© NXP B.V. 2010. All rights reserved.
Section
BASE_USB_CLK
BASE_USB_I2C_CLK
BASE_OUT_CLK
002aae148
below.
6.16.2.2).
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