STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 155

• Manufacturer Part Number: STM32W108CZ
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CZ

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Bits [11:8] TIM_ETF: External Trigger Filter
Bits [6:4] TIM_TS: Trigger Selection
Bits [2:0] TIM_SMS: Slave Mode Selection
Bit 7 TIM_MSM: Master/Slave Mode
This defines the frequency used to sample the ETRP signal, f
digital filter applied to ETRP. The digital filter is made of an event counter in which N events are
needed to validate a transition on the output:
0000: f
0001: f
0010: f
0011: f
0100: f
0101: f
0110: f
0111: f
Note: PCLK is 12 MHz when the STM32W108 is using the 24 MHz crystal oscillator, and 6
0: No action.
1: The effect of an event on the trigger input (TRGI) is delayed to allow exact synchronization
between the current timer and the slave (through TRGO). It is useful for synchronizing timers
on a single external event.
This bit field selects the trigger input used to synchronize the counter.
000 : Internal Trigger 0 (ITR0).
100 : TI1 Edge Detector (TI1F_ED).
101 : Filtered Timer Input 1 (TI1FP1).
110 : Filtered Timer Input 2 (TI2FP2).
111 : External Trigger input (ETRF).
Note: These bits must be changed only when they are not used (when TIM_SMS=000) to
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input.
000: Slave mode disabled.
If TIM_CEN = 1 then the prescaler is clocked directly by the internal clock.
001: Encoder mode 1. Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
010: Encoder mode 2. Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
011: Encoder mode 3. Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
on the level of the other input.
100: Reset Mode. Rising edge of the selected trigger signal (TRGI) >reinitializes the counter
and generates an update of the registers.
101: Gated Mode. The counter clock is enabled when the trigger signal (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both starting and stopping
the counter are controlled.
110: Trigger Mode. The counter starts at a rising edge of the trigger TRGI (but it is not reset).
Only starting the counter is controlled.
111: External Clock Mode 1. Rising edges of the selected trigger (TRGI) clock the counter.
Note: Gated mode must not be used if TI1F_ED is selected as the trigger input
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
MHz if using the 12 MHz RC oscillator.
avoid detecting spurious edges during the transition.
(TIM_TS=100). TI1F_ED outputs 1 pulse for each transition on TI1F, whereas gated
mode checks the level of the trigger signal.
= PCLK/2, N=8.
= PCLK/4, N=8.
= PCLK, no filtering.
= PCLK, N=2.
= PCLK, N=4.
= PCLK, N=8.
= PCLK/2, N=6.
= PCLK/4, N=6.
Doc ID 16252 Rev 13
1111: f
1110: f
1101: f
1100: f
1011: f
1010: f
1001: f
1000: f
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
Sampling
= PCLK/32, N=6.
= PCLK/32, N=5.
= PCLK/16, N=8.
= PCLK/16, N=6.
= PCLK/16, N=5.
= PCLK/8, N=8.
= PCLK/8, N=6.
= PCLK/32, N=8.
General-purpose timers
, and the length of the
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