STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 81

• Manufacturer Part Number: STM32W108CZ
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CZ

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Note:
9.3.3
Characters received are stored in the receive FIFO. Receiving characters sets the
SC_SPIRXVAL bit in the SCx_SPISTAT register, indicating that characters can be read from
the receive FIFO. Characters received while the receive FIFO is full are dropped, and the
SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware
generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the receive FIFO is drained. Once the DMA marks a receive error, two
conditions will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in
the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.
To receive a character, you must transmit a character. If a long stream of receive characters
is expected, a long sequence of dummy transmit characters must be generated. To avoid
software or transmit DMA initiating these transfers and consuming unnecessary bandwidth,
the SPI serializer can be instructed to retransmit the last transmitted character or to transmit
a busy token (0xFF), which is determined by the SC_SPIRPT bit in the SCx_SPICFG
register. This functionality can only be enabled or disabled when the transmit FIFO is empty
and the transmit serializer is idle, indicated by a cleared SC_SPITXIDLE bit in the
SCx_SPISTAT register.
Every time an automatic character transmission starts, a transmit underrun is detected as
there is no data in transmit FIFO, and the INT_SCTXUND bit in the INT_SC2FLAG register
is set. After automatic character transmission is disabled, no more new characters are
received. The receive FIFO holds characters just received.
The Receive DMA complete event does not always mean the receive FIFO is empty.
The DMA Channels section describes how to configure and use the serial receive and
transmit DMA channels.
Interrupts
SPI master controller second level interrupts are generated by the following events:
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To enable CPU interrupts, set the desired interrupt bits in the second level INT_SCxCFG
register, and enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit in the
INT_CFGSET register.
Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE,
either the 0 to 1 transition or the high level of SC_SPITXIDLE)
Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0
to 1 transition or the high level of SC_SPITXFREE)
Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either
the 0 to 1 transition or the high level of SC_SPIRXVAL)
Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)
Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)
Received and lost character while receive FIFO was full (receive overrun error)
Transmitted character while transmit FIFO was empty (transmit underrun error)
Doc ID 16252 Rev 13
Serial interfaces
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