FMS6143CSX Fairchild Semiconductor, FMS6143CSX Datasheet - Page 9

• Manufacturer Part Number: FMS6143CSX
• Description: IC DRIVER VIDEO FILTER 3CH 8SOIC
• Manufacturer: Fairchild Semiconductor
• Type: Video Filterr

Specifications of FMS6143CSX

• Applications: DVD, HD, Set-Top Boxes, Recorders
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Video Signal Filter: SD
• Frequency: 27MHz
• Bandwidth: 7.7MHz
• Attenuation: 48dB
• Filter Order: 4th
• Supply Voltage Range: 4.75V To 5.25V
• Tv / Video Case Style: SOIC
• No. Of Pins: 8
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FMS6143CSXTR; FMS6143CSX_NL; FMS6143CSX_NLTR; FMS6143CSX_NLTR

© 2006 Fairchild Semiconductor Corporation
FMS6143 • Rev. 4.0.8
Layout Considerations
General layout and supply bypassing play a major role in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board to guide layout and
aid device evaluation. The demo board is a four-layer board
with full power and ground planes. Following this layout con-
fi guration provides optimum performance and thermal
characteristics for the device. For the best results, follow the
steps and recommended routing rules listed below.
Recommended Routing/Layout Rules
■
■
■
■
■
■
■
■
■
■
■
■
Thermal Considerations
Since the interior of most systems, such as set-top boxes,
TVs, and DVD players, are at +70ºC; consideration must be
given to providing an adequate heat sink for the device pac-
kage for maximum heat dissipation. When designing a sys-
tem board, determine how much power each device dissipa-
tes. Ensure that devices of high power are not placed in the
same location, such as directly above (top plane) or below
(bottom plane), each other on the PCB.
PCB Thermal Layout Considerations
■
■
Do not run analog and digital signals in parallel.
Use separate analog and digital power planes to supply
power.
Traces should run on top of the ground plane at all times.
No trace should run over ground/power splits.
Avoid routing at 90-degree angles.
Minimize clock and video data trace length differences.
Include 10μF and 0.1μF ceramic power supply bypass
capacitors.
Place the 0.1μF capacitor within 0.1 inches of the device
power pin.
Place the 10μF capacitor within 0.75 inches of the device
power pin.
For multi-layer boards, use a large ground plane to help
dissipate heat.
For two-layer boards, use a ground plane that extends
beyond the device body at least 0.5 inches on all sides.
Include a metal paddle under the device on the top layer.
Minimize all trace lengths to reduce series inductance.
Understand the system power requirements and
environmental conditions.
Maximize thermal performance of the PCB.
9
■
■
■
■
■
Output Considerations
The FMS6143 outputs are DC offset from the input by
150mV. Therefore, V
required to obtain optimal performance from the output dri-
ver and is held at the minimum value to decrease the stan-
ding DC current into the load. Since the FMS6143 has a 2x
(6dB) gain, the output is typically connected via a 75Ω-series
back-matching resistor, followed by the 75Ω video cable.
Due to the inherent divide by two of this confi guration, the
blanking level at the load of the video signal is always less
than 1V. When AC-coupling the output, ensure that the
coupling capacitor of choice passes the lowest frequency
content in the video signal and that line time distortion (video
tilt) is kept as low as possible.
The selection of the coupling capacitor is a function of the
subsequent circuit input impedance and the leakage current
of the input being driven. To obtain the highest quality output
video signal, the series termination resistor must be placed
as close to the output pin as possible. This reduces the para-
sitic capacitance and inductance effect on the output driver.
The distance from the device pin to the series termination
resistor should be no greater than 0.1 inches.
Consider using 70μm of copper for high-power designs.
Make the PCB as thin as possible by reducing FR4
thickness.
Use vias in power pad to tie adjacent layers together.
Remember that baseline temperature is a function of
board area, not copper thickness.
Modeling techniques provide a fi rst-order approximation.
Figure 18. Distance from Device Pin to Series
Termination Resistor
OUT
= 2•V
IN
DC+150mV. This offset is
www.fairchildsemi.com