TMP91xy16FG Toshiba, TMP91xy16FG Datasheet
TMP91xy16FG
Specifications of TMP91xy16FG
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TMP91xy16FG Summary of contents
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... TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C016FG JTMP91C016S Semiconductor Company ...
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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • ...
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Built-in RAM: None Built-in ROM: None (4) External memory expansion • Expandable up to 105 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus: Dynamic data bus sizing • Separate bus system (5) 8-bit timers: ...
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... Slow mode (fs = 32.768 kHz) (21) Operating voltage • VCC = 2 3.6 V (fc max = 27 MHz) • VCC = 1 3.6 V (fc max = 10 MHz) (22) Package • 100-pin QFP: LQFP100-P-1414-0.50F • Chip form supply also available. For details, contact your local Toshiba sales representative. 91C016-3 TMP91C016 2008-02-20 ...
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VLD0 to VLD2 VLD0,1,2 (Detecter) (PB0 to PB2) VLDVCC, GND VREF TXD1 (PC3) SIO/UART RXD1 (PC4) (SIO1) SCLK1/ (PC5) CTS1 SIO/UART/IrDA OPTRX0 (P72) (SIO0) OPTTX0 (P71) 8-bit timer (TMRA0) 8-bit timer TA1OUT/SCOUT (P70) (TMRA1) 8-bit timer (TMRA2) 8-bit timer (TMRA3) ...
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Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C016, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C016FG. VLD2/PB2 1 VLDGND VLDVCC KI0/P90 KI1/P91 ...
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Pad Layout (Chip size 4.38 mm × 4.43 mm) Pin Name X Point Y Point No −2057 1 PB2 1531 −2057 2 VLDGND 1417 −2057 3 VLDVCC 1303 −2057 4 P90 990 −2057 5 P91 876 −2057 6 P92 ...
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Pin Names and Functions The names of the input/output pins and their functions are described below. Number Pin Name I/O of Pins I/O P10 to P17 8 I D15 I/O P20 to P27 ...
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Number Pin Name I/O of Pins P70 1 I/O SCOUT Output TA1OUT Output P71 1 I/O OPTTX0 Output Output CS2D P72 1 I/O OPTRX0 Input Output CS2E P73 1 I/O Output DRAMOE Output EXRD P74 1 I/O Input NMI Output ...
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Number Pin Name I/O of Pins PD0 1 I/O D1BSCP Output PD1 1 I/O D2BLP Output PD2 1 I/O D3BFR Output PD3 1 I/O DLEBCD Output PD4 1 I/O DOFFB Output PD6 1 I/O Output ALARM Output MLDALM PD7 1 ...
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Operation This following describes block by block the functions and operation of the TMP91C016. Notes and restrictions for eatch book are outlined in 6. “Points of Note and Restrictions” at the end of this manual. 3.1 CPU The TMP91C016 ...
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Read Figure 3.1.1 TMP91C016 Reset Timing Chart 91C016-11 TMP91C016 Write 2008-02-20 ...
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Memory Map Figure 3.2 memory map of the TMP91C016. 000000H Internal I/O (4 Kbytes) 000100H 000FE0H 000FE7H 010000H External memory FFFF00H Vector table (256 bytes) FFFFFFH Note: Address 000FE0H to 00FE7H are assigned for the external memory ...
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Triple Clock Function and Standby Function TMP91C016 contains (1) clock gear, (2) clock doubler (DFM), (3) standby controller and (4) noise-reduction circuit used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of ...
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The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (the X1, X2, XT1 and XT2 pins and DFM). Figure ...
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Block Diagram of System Clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> DFMCR0<ACT1:0, DLUPTM> Warm-up timer (High-/Low-frequency oscillator), Lockup timer (DFM) SYSCR0 <XTEN, RXTEN> XT1 Low-frequency fs oscillator XT2 = f f DFM OSCH SYSCR0 <XEN, RXEN> Clock doubler (DFM) X1 High-frequency oscillator X2 ...
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SFRs 7 6 SYSCR0 Bit symbol XEN XTEN (00E0H) Read/Write After reset 1 1 High- Low- Function frequency frequency oscillator (fc) oscillator (fs) 0: Stop 0: Stop 1: Oscillation 1: Oscillation 7 6 Bit symbol SYSCR1 (00E1H) Read/Write After ...
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Symbol Name Address 7 ACT1 R/W 0 DFM DFM DFMCR0 Control E8H 00 STOP STOP Register 0 01 RUN 10 RUN STOP 11 RUN STOP D7 R/W DFM 0 DFMCR1 Control E9H Register 1 Limitation point on the use of ...
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EMCCR0 Bit symbol PROTECT (00E3H) Read/Write R R/W After reset 0 0 Function Protect flag Always Write “0” 0: OFF 1: ON EMCCR1 Bit symbol (00E4H) Read/Write Switching the protect ON/OFF by write to following 1st key, ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc ...
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Example 1: Setting the clock Changing from high frequency (fc) to low frequency (fs). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H (SYSCR2), X − 11 − − X − SET 6, (SYSCR0) SET 2, (SYSCR0) WUP: ...
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Example 2: Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H (SYSCR2), X − 10 − − X − SET 7, (SYSCR0) SET 2, (SYSCR0) WUP: ...
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Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> set according to the contents of the clock gear select register SYSCR1<GEAR0:2> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the ...
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Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1, SBI) there is a prescaler which can divide the clock. The φT clock input to the prescaler is either the clock f divided by 2. The ...
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Limitation point on the use of DFM 1. It’s prohibited to execute DFM enable/disable control in the SLOW mode (fs) (Write to DFMCR0<ACT1:0> = “10”). You should control DFM in the NORMAL mode you stop DFM operation during ...
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Change/stop control (OK) DFM use mode (f DFM (f ) → DFM stop → Low-frequency oscillator operation mode (fs) → OSCH High-frequency oscillator stop LD (DFMCR0 Change the system ...
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Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents ...
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Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Resonator C2 XT2 pin (Setting method) The drivability of EMCCR0<DRVOSCL> register. By reset, <DRVOSCL> is initialized to ...
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Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that the state which is fetch ...
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Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When write operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. ...
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Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: ...
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How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. ...
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Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT mode NMI INTWD INT0 to INT3 (Note 1) INTALM0 to INTALM4 INTTA0 to INTTA3 INTRX0 to INTRX1, TX0 to TX1 INTKEY INTRTC INTLCD *2 ...
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Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of ...
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STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<DRVE> register. Table 3.3.7, Table 3.3.8 summarizes the state of these pins in ...
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Example: The STOP mode is entered when the low frequency operates, and high-frequency operates after releasing due to NMI. Address SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H 8FFDH LD (SYSCR1), 08H (SYSCR2), X − 1001X1B 9000H LD (SYSCR0), ...
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Input Function Port Name During When Name Reset Used as function – D0-7 ON upon external OFF P10-17 D8-15 P52(*1) INT3 P53(*1) WAIT ON P56(*1) MSK – P60-67(*1) OFF – P70-71(*1) P72(*1) OPTRX0 ON – P73(*1) OFF P74(*1) NMI P90-97(*1) ...
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Table 3.3.8 Output buffer State Table Output Function Port Name During Name Reset D0-D7 – OFF P10-17 D8-15 P20-27 A16-23 A0-15 – ON – RD – WR P52(*1) HWR P53(*1) EXWR P56(*1) R/W OFF P60(*1) ,LCLK0 CS 0 P61(*1) CS ...
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Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C016 has a total of 40 interrupts divided into the following three types: • Interrupts generated by CPU: 9 sources (Software ...
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Interrupt processing Interrupt specified by micro DMA start vector? No Interrupt vector value “V” read Interrupt request F/F clear General-purpose PUSH PC interrupt PUSH SR processing SR<IFF2:0> ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 PC ...
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General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the ...
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Table 3.4.1 TMP91C016 Interrupt Vectors Table Default Interrupt Source and Source of Type Priority 1 Reset or SWI 0 instruction 2 SWI 1 instruction 3 INTUNDEF: Illegal instruction or SWI 2 instruction 4 SWI 3 instruction 5 SWI 4 instruction ...
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Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C016 supports a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable interrupts, regardless of the ...
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Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA ...
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Soft start function In addition to starting the micro DMA function by interrupts, TMP91C016 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing “1” to ...
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Detailed description of the transfer mode register 8 bits DMAM0 Mode to DMAM3 Number of Transfer Bytes 000 000 00 Byte transfer Transfer destination address INC mode (Fixed) .................................................I/O to memory (DMADn+) ← (DMASn) 01 Word ...
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Interrupt Controller Operation The block diagram inFigure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For ...
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Figure 3.4.3 Block Diagram of Interrupt Controller 91C016-47 TMP91C016 2008-02-20 ...
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Interrupt priority setting registers Symbol Name Address 7 INT0 INTE0 90H enable INT1 and I2C INT2 INTE12 91H R enable 0 INT3 and IA4C INTALM4 92H INTE3ALM4 R enable 0 INTALM0 and IA1C 93H INTEALM01 INTALM1 R enable 0 ...
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Symbol Name Address 7 Interrupt ITX0C enable INTES0 98H R serial 0 0 INTRX1 and ITXT1C INTES1 99H INTTX1 R enable 0 ILCD1C INTLCD 9AH INTELCD enable R 0 INTTC0 and ITC1C 9BH INTETC01 INTTC1 R enable 0 INTTC2 ITC3C ...
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External interrupt control Symbol Name Address 7 – 8CH Interrupt 0 input IIMC Always Always mode (Prohibit write “0” write “0” control RMW) INT0 level enable 0 Edge detect INT 1 H level INT rising edge enable NMI 0 ...
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Symbol Name Address 7 DMA0 DMA0V start 80H vector DMA1 DMA1V start 81H vector DMA2 DMA2V start 82H vector DMA3 DMA3V start 83H vector (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until ...
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Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may ...
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Port Functions The TMP91C016 features 57-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 ...
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Table 3.5.2 I/O Registers and Specifications (1/2) Port Pin Name Port 1 P10 to P17 Input port (Note 1) Output port D8 to D15 bus Port 2 P20 to P27 Output port A16 to A23 output Port 5 P52, P53, ...
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Table 3.5.3 I/O Registers and Specifications (2/2) Port Pin Name Specification Port 9 P90 to P97 Input port KI0 to KI7 input Port B PB0 to PB5 Input port Output port PB0 VLD0 input (Note 12) PB1 VLD1 input (Note ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting, the control register P1CR to 0 and sets Port 1 ...
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Port 2 (P20 to P27) Port 8-bit output port. In addition to functioning as a output port, port 2 can also function as an address bus (A16 to A23). Each bits can be set individually for ...
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Bit symbol P17 P16 P1 P0 (0001H) (0000H) Read/Write After reset Data from external port (Output latch register is cleared to 0 Bit symbol P17C P16C P1CR (0004H) Read/Write After reset 0/1 0/1 (Note) Function 7 ...
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Port 5 (P52, P53, P56) Port 3-bit general-purpose I/O port. This I/O port is set using control register P5CR, P5FC, P5FC2 and P5UDE. And P52 port have have input, WAIT EXWR function. Resetting resets all bits ...
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Reset Pull-up resistor control (on bit basis) P5UDE write Direction control (on bit basis) P5CR write Function control (on bit basis) P5FC write Output latch B Output buffer P5 write EXWR P5 read Internal WAIT Reset Pull-up ...
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Bit symbol P56 P5 (000DH) Read/Write After reset 7 6 Bit symbol P56C P5CR (000AH) Read/Write After reset 0 Function 7 6 Bit symbol P56F P5FC (000BH) Read/Write After reset 0 Function 0: Port ...
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Port 6 (P60, P61, P63 to P67) Port 6 is 7-bit I/O port. This I/O port have standard chip select signal output function ( , , ), expand address signal output function (EA24, EA25), expand chip select CS0 CS1 ...
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Bit symbol P67 P66 P6 (0012H) Read/Write After reset 7 6 Bit symbol P67C P66C P6CR (0014H) Read/Write After reset Function 0: Input 7 6 Bit symbol P67F P66F P6FC (0015H) Read/Write After reset Function 0: Port 0: ...
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Port 7 (P70 to P74) Port 7 is 5-bit general-purpose I/O port. This port can be set I/O on bit basis. Resetting resets all bits of P7CR, P7FC and P7FC2 to P7FC0, and become to input port, and all ...
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Port 70 (SCK, OPTRX0) Port general-purpose I/O port also used as TA1OUT (8-bit timer output function) and SCOUT (Internal clock output function). In case of used as TA1OUT, it set to P7FC<P70F> ...
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Port OPTTX0) CS2D Port 71 also function as extend chip-select output ( for IrDA mode of SIO0 (OPTTX0). When P71 is used to OPTTX0 function, it possible to control logical reverse by P7<P71>. Setting to P7UDE<P71U> ...
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Port OPTRX0) CS2E Port 72 have also function as extend chip-select output ( for IrDA mode of SIO0 (OPTRX0). When P72 is used to OPTRX0 function, it possible to control logical reverse by P7<P72>. Selection of ...
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Port EXRD DRAMOE Port 73 have also function as DRAM control output ( output ( ). output same timing as EXRD EXRD Setting to P7UDE<P73U> set to pull-up resistor. It become to pull-up ...
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Port NMI CAS WE Port 74 have also function NMI And setting P7UDE<P74U> set to pull-up resistor. It become to pull-up situation by reset operation. Reset Pull-up resistor control (on bit basis) ...
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P7 Bit symbol (0013H) Read/Write After reset 7 6 P7CR Bit symbol (0016H) Read/Write After reset Function 7 6 Bit symbol P7FC (0017H) Read/Write After reset Function 7 6 Bit symbol P7FC2 (001CH) Read/Write After reset Function Port ...
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Port 9 (P90 to P97) Port are 8-bit input ports with pull-up resistors. In addition to functioning as general-purpose I/O port, port can also key-on wakeup function as keyboard interface. The various functions ...
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Bit symbol P97 P96 P9 (0019H) Read/Write After reset 7 6 Bit symbol P97F P96F P9FC Read/Write (001DH) After reset 0 0 Function 7 6 Bit symbol P97U P96U P9UE Read/Write (001EH) After reset Function Pull-up Pull-up resistor ...
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Port B (PB0 to PB5) Port B is 6-bit general-purpose I/O port. This I/O port have voltage level detector function (VLD0 to VLD2), external interrupt input function (INT0 to INT2). It can be controlled by IIMC register’s setting to ...
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PB3 (INT0) Reset Pull-up resistor control (on bit basis) PBUDE write Direction control (on bit basis) PBCR write Function control (on bit basis) PBFC write S Output latch write read INT0 Level/edge select ...
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Bit symbol PB (0022H) Read/Write After reset 7 6 Bit symbol PBCR (0024H) Read/Write After reset Function 7 6 Bit symbol PBFC Read/Write (0025H) After reset Function Port B Pull-up/Pull-down Resistor Control Register 7 6 Bit symbol PB5UD ...
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Port C (PC3 to PC5, PC6, PC7) Port C is 5-bit general-purpose I/O port. By reset, these ports become to input port and set all output latch. Except I/O port function, this port have serial channel ...
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Port C4 (RXD1) Port C4 have also function as serial channel input (RXD1). When it used to RXD1 function, it possible to out logical reverse by PC<PC4> register setting. Port C4 can set pull-up or pull-down resistor by writing ...
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Port SCLK1) CTS1 Port C5 have also function as serial channel I/O ( (SCLK1). When it used to serial channel port, it possible to set logical reverse I/O by PC<PC5>. Port C5 can set pull-up or ...
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Port C6 (XT1), C7 (XT2) Port C6, C7 have low-frequency oscillator function, except I/O port function. Reset S Direction control (on bit basis) PCCR write S Output latch PC write S Selector Y PC read S Direction control (on ...
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Bit symbol PC7 PC6 PC (0023H) Read/Write R/W Function Data from external port (Output latch register is set Bit symbol PC7C PC6C PCCR (0026H) Read/Write W W After reset 1 1 Function 0: Input ...
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Port D (PD0 to PD4, PD6, PD7) Port D is 7-bit general-purpose I/O port. And port D0 to D4, D6, D7 can be set pull-up resistor by setting 1 data correspond bit of PDUE register. Port ...
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PD4 (DOFFB) Reset Pull-up resistor control (on bit basis) PDUDE write Direction control (on bit basis) PDCR write Function control (on bit basis) PDFC write S Output latch DOFFB PD write read Figure 3.5.27 ...
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Bit symbol PD7 PD6 PD (0029H) Read/Write R/W After reset 7 6 Bit symbol PD7C PD6C PDCR (002BH) Read/Write W After reset 0 Function 0: Input 1: Output 7 6 Bit symbol PD7F PD6F PDFC (002AH) Read/Write W ...
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Chip Select/Wait Controller On the TMP91C016, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The ...
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Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper eight bits (A23 to A16) of ...
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Memory address mask registers Figure 3.6.3 shows the memory address mask registers. The memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit ...
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Setting memory start addresses and address areas Figure 3.6.4 show an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0<S23:16> (Corresponding to the upper 8 bits ...
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Address area size specification Table 3.6.1 shows the relationship between CS area and area size. The triangle (∆) indicates in the table below that areas cannot be set by memory start address register and address mask register combinations. When ...
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Chip Select/Wait Control Register 7 6 B0CS Bit symbol B0E (00C0H) Read/Write W After reset 0 Read- 0: Disable modify- Function 1: Enable write instructions are prohibited. B1CS Bit Symbol B1E (00C1H) Read/Write W After reset 0 Read- 0: Disable ...
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Master enable bits Bit7 (<B0E>, <B1E>, <B2E> or <B3E> chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables the ...
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Wait control Bits (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2> chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait ...
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Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: 1. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. 2. ...
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Connecting External Memory Figure 3.6.6 shows an example of how to connect external memory to the TMP91C016. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C016 ...
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Timers (TMRA) The TMP91C016 features 4 channel (TMRA0 to TMRA3) built-in 8-bit timers. These timers are paired into 2 modules: TMRA01 and TMRA23. Each module consists of 2 channels and can operate in any of the following 4 ...
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Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 91C016-95 TMP91C016 2008-02-20 ...
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Figure 3.7.2 TMRA23 Block Diagram 91C016-96 TMP91C016 2008-02-20 ...
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Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The “φT0” as the input clock to pre-scaler is a clock divided by 4 which selected using the prescaler clock selection register SYSCR0<PRCK1:0>. The ...
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Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator ...
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Comparator (CP0) The comparator compares the value counter with the value set in a timer register. If they match, the up counter is cleared to “0” and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFRs 7 6 TA01RUN Bit symbol TA0RDE (0100H) Read/Write R/W After reset 0 Function Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN ...
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TA01MOD Bit symbol TA01M1 TA01M0 (0104H) Read/Write After reset 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA01 Mode Register PWM01 PWM00 ...
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TA23MOD Bit symbol TA23M1 TA23M0 (010CH) Read/Write After reset 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA23 Mode Register PWM21 PWM20 ...
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TA1FFCR Bit symbol (0105H) Read/Write After reset Function Read- modify- write instructions are prohibited. TMRA1 Flip-Flop Control Register TA1FFC1 TA1FFC0 R/W 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care Inverse ...
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TA3FFCR Bit symbol (010DH) Read/Write After reset Function Read- modify- write instructions are prohibited. TMRA3 Flip-Flop Control Register TA3FFC1 TA3FFC0 W 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care Inverse ...
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TA0REG bit Symbol (0102H) Read/Write After reset TA1REG bit Symbol (0103H) Read/Write After reset TA2REG bit Symbol (010AH) Read/Write After reset TA3REG bit Symbol (010BH) Read/Write After reset Note: The avobe registers are prohibited read-modify-write instruction. Timer register ...
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Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Setting its function or counter data for TMRA0 and TMRA1 after stop these registers. a. Generating interrupts at a ...
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Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.8-µs square wave pulse from ...
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Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter 1 2 ...
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A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD<TA01M1:0> to “01”. In 16-bit timer ...
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PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active-low or active-high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses ...
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In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be ...
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Example: To generate 1/4-duty 50-kHz pulses ( MHz): 20 µs * Clock state Calculate the value which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: ...
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PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output ...
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In this mode, the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match ...
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Select System Select Prescaler Gear Value Clock Clock <GEAR2:0> <SYSCK> <PRCK1:0> 1 (fs) XXX 000 (fc) 001 (fc/ FPH 010 (fc/4) 0 (fc) 011 (fc/8) 100 (fc/16) 10 XXX (fc/16 clock) XXX: Don’t care (5) Settings for ...
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MELODY/ALARM circuit supply mode This function can operate only TMRA3. It can use MELODY/ALARM souce clock TA3 clock generated by TMRA3. But this function is special mode, without low clock (XTIN, XTOUT), so keep the rule under below. OPERATE ...
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External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 105 Mbytes by having 4 local area. Address pins to external memory are 2 extended address bus pins (EA24, EA25) and 5 extended chip ...
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Recommendable Memory Map The recommendation logic address memory map at the time of varieties extension memory correspondence is shown in Figure 3.8.1. And, a physical-address map is shown in Figure 3.8.2. However, when memory area is less than 16 ...
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LOCAL0 TMP91C016 CS3 for data RAM (8 Mbytes: SRAM and DRAM) BANK0 000000H BANK1 BANK2 BANK3 BANK4 Internal-I/O and RAM BANK5 BANK6 BANK7 800000H 1000000H : Internal area : Overlapped with common area Figure 3.8.2 Physical Address Map LOCAL1 LOCAL2 ...
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Operational Description Set up bank value and bank use in bank setting-register of each local area of local register in common area. Moreover, in that case, a combination pin is set up and mapping is simultaneously set up by ...
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CS0 CS1 Data Address TMP91C016 , : SRAM UDS LDS , , RD WR HWR CS2 EA24, EA25 CS3 * 16 bits TMP91C016 Memory Control signals Control signals D [0:15] D [0:15] A0 Open ...
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LD (MSAR0), 00H ; Logical address area: 000000H to 1FFFFFH LD (MAMR0), 7FH ; Logical address size: 1 Mbyte LD (B0CS), 81H ; Condition: 16 bits,1wait (8 Mbytes, SRAM) ;CS1 LD (MSAR1), 40H ; Logical address area: ...
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CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG a00000H ORG c00000H ORG E00000H LD (Local 3), 85H LDW HL, (800000H) LD (Local 3), 88H LDW BC, (800000H) ~ ORG FFFFFFH CS3 ;***** ...
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CS2 ORG 000000H ; Program ROM: Start address at BANK0 OF LOCAL2 ORG 200000H ; Program ROM: Start address at BANK1 of LOCAL2 NOP ; Operation at BANK1 of LOCAL2 ~ JP E00100H ; Jump to ...
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At Figure 3.8.7, it shows example of program jump. In the same way with before example, two dot line squares show each ROM and ’s option ROM. Program start from E00000H common address, firstly, write CS1 to bank register of ...
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Serial Channels TMP91C016 includes 2 serial I/O channels. We call each channels, one is SIO0 and another is SIO1. SIO0 channel can selected either UART mode (Asynchronous transmission) or IrDA mode (Infrared rays transmission). And SIO1 channel can selected ...
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Mode 0 (I/O interface mode) Bit0 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 Start Bit0 Parity 1 2 • Mode 2 (8-bit UART mode) No parity Start Bit0 1 ...
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Block Diagrams Figure 3.9 block diagram representing serial channel 0. Prescaler φ φT2 φT8 φT32 Serial clock generation circuit BR0CR <BR0CK1:0> BR0CR BR0ADD <BR0S3:0> <BR0K3:0> φT0 φT2 φT8 φT32 BR0CR <BR0ADDE> ...
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Prescaler φ φT2 φT8 φT32 Serial clock generation circuit BR1CR <BR1CK1:0> BR1CR BR1ADD <BR1S3:0> <BR1K3:0> φT0 φT2 φT8 φT32 BR1CR <BR1ADDE> Baud rate generator f SYS SCLK1 Concurrent with PC5 I/O interface mode SCLK1 ...
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Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR<PRCK1:0> is divided by 4 and input to the prescaler as φT0. The prescaler can be run by ...
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Baud rate generator The baud rate generator is a circuit, which generates transmission and receiving clocks, which determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is ...
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Integer divider (N divider) For example, when the source clock frequency (fc) = 12.288 MHz, the input clock frequency = φT2 (fc/16), the frequency divider N (BR1CR<BR1S3:0> and BR1CR<BR1ADDE> the baud rate in UART mode ...
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Table 3.9.3 Transfer Rate Selection (when baud rate generator Is used and BR1CR<BR1ADDE> Input Clock Frequency Divider fc [MHz] (set to BR1CR<BR1S3:0>) 9.830400 2 ↑ 4 ↑ 8 ↑ 0 12.288000 5 ↑ A 14.745600 2 ↑ 3 ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC1CR<IOC> the basic clock is generated by dividing the output ...
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The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When bits ...
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Handshake function Use of pin allows data can be sent in units of one frame; thus, overrun errors CTS1 can be avoided. The handshake functions is enabled or disabled by the SC1MOD<CTSE> setting. When the pin goes high on completion ...
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Transmission buffer The transmission buffer (SC1BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates ...
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Timing generation a. In UART mode Receiving Mode 9 Bits Interrupt timing Center of last bit (Bit8) Framing error timing Center of stop bit Parity error timing – Overrun error timing Center of last bit (Bit8) Note: In 9-Bit ...
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SFRs 7 Bit symbol TB8 SC0MOD0 (0202H) Read/Write After reset 0 Function Transfer Always data bit8 write 0 Figure 3.9.7 Serial Mode Control Register (SIO0, SC0MOD0 – – RXE SM1 R ...
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Bit symbol TB8 CTSE SC1MOD0 Read/Write (020AH) After reset 0 Function Transfer Handshake data bit8 0: CTS disable 1: CTS enable Figure 3.9.8 Serial Mode Control Register (SIO1, SC1MOD0 RXE WU SM1 R ...
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Bit symbol RB8 EVEN SC0CR (0201H) Read/Write R After reset Undefined 0 Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with ...
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SC1CR Bit symbol RB8 EVEN (0209H) Read/Write R After reset Undefined 0 Function Received Parity data bit8 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with ...
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BR0CR Bit symbol BR0ADDE (0203H) Read/Write After reset 0 0 Function Always +(16 − K)/16 write 0 division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disable 1 Enable 7 6 BR0ADD Bit symbol ...
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Bit symbol BR1ADDE BR1CR (020BH) Read/Write After reset 0 0 Function Always + (16 − K)/16 write 0 division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disabled 1 Enabled 7 6 BR1ADD Bit ...
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TB7 TB6 TB5 SC0BUF (0200H RB7 RB6 RB5 Note: Prohibit read modify write for SC0BUF. Figure 3.9.13 Serial Transmission/Receiving Buffer Registers (SIO0, SC0BUF) 7 Bit symbol I2S0 FDPX0 SC0MOD1 (0205H) Read/Write R/W R/W After ...
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TB7 TB6 TB5 SC1BUF (0208H RB7 RB6 RB5 Note: Prohibit read modify write for SC1BUF. Figure 3.9.15 Serial Transmission/Receiving Buffer Registers (SIO1, SC1BUF) 7 Bit symbol I2S1 FDPX1 SC1MOD1 (020DH) Read/Write R/W R/W After ...
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Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD1 and SCLK1 pins respectively each time the CPU writes the data to the transmission buffer. When all data is output, INTES1<ITX1C> will be ...
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Receiving In SCLK output mode, the synchronous clock is outputted from SCLK1 pin and the data is shifted to receiving buffer 1. This starts when the Receive Interrupt flag INTES1<IRX1C> is cleared by reading the received data. When 8-bit ...
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Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to 0 and set enable the interrupt level ( the transfer interrupt. In the transfer interrupt program, ...
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Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting serial channel SC1MOD0<SM1:0> to 01. In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of ...
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Clock state Main settings ← − − − 0 − PCCR SC1MOD0 ← − ← ...
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Protocol a. Select 9-bit UART mode on the master and slave controllers. b. Set the SC1MOD0<WU> bit on each slave controller enable data receiving. c. The master controller transmits one-frame data including the 8-bit select code for ...
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Example: To link two slave controllers serially with the master controller using the internal clock f TXD RXD Master • Setting the master controller Main ← − − − PCCR ← − X ...
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Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.24 shows the block diagram. Transmisison data IR modulator SIO0 Modem Receive data IR demodulator TMP91C016 Figure 3.9.24 IrDA Block Diagram (1) Modulation of ...
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Data format The data format is fixed as follows: • Data length: 8 bits • Parity bits: none • Stop bits can’t guarantee the correct operation in any other setting. (4) SFR Figure 3.9.27 shows the control ...
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As the same reason, + (16 − K)/16 division function in the baud rate generator of SIO0 can not be used to generate 115.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 ...
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SIRCR Bit symbol PLSEL RXSEL (0207H) Read/Write After reset 0 0 Select Receive Function transmit data pulse 0: H pulse width 1: L pulse 0: 3/16 1: 1/16 Figure 3.9.27 IrDA Control Register TXEN ...
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DRAM Controller TMP91C016 incorporates a 1-channel DRAM controller for interface with × 8-/16-bit DRAM. The DRAM controller consists of a control circuit to refresh the DRAM, an access circuit for reading and writing, and a row/column address multiplexer. 1) ...
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Bit symbol DMI RS2 DREFCR (0430H) Read/Write After reset 0 0 Function Dummy Refresh cycle insertion interval cycle 0: Disable 1: Dummy cycle Figure 3.10.1 Refresh Control Register DREFCR1 Register RS1 RS0 RW2 RW1 ...
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DMEMCR Bit symbol SRFC - (0431H) Read/Write W After reset 1 0 Function Self- Always Read refresh Write 0 -modify -write 0: Self- instruction refresh is prohibited 1: Self- refresh release Figure 3.10.2 DRAM Memory Access Control Register ...
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Description of Operation TMP91C016 has a one-channel internal DRAM controller. This channel is normally linked to CS3 of the CS/WAIT controller. The DRAM controller generates the DRAM access cycle. The DRAM signals share pins with port 6 and port ...
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Refresh control block TMP91C016 outputs the refreshing DRAM. When using an 8-bit bus, the device also outputs state signal to indicate a refresh cycle. REFOUT As the output cycle and pulse width of the set by program, the DRAM ...
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CAS RAS This mode is used when the clock supplied to the DRAM controller is stopped by a HALT instruction (IDLE, STOP) while refreshing using the refresh mode. To refresh DRAM in -before- interval refresh mode. Then, ...
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Connection Example TMP91C016 DRAMOE WE RAS CAS Table 3.10.4 8-Bit Bus Configuration TMP91C016 D0 to D15 DRAMOE WE RAS LCAS UCAS Table 3.10.5 16-Bit Bus Configuration DRAM I/ ...
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Watchdog Timer (Runaway detection timer) The TMP91C016 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (Runaway) due ...
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The watchdog timer consists of a 22-stage binary counter which uses the system clock ( the input clock. The binary counter can output f SYS SYS WDT counter n WDT interrupt WDT clear (Software) ...
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Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting ...
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WDMOD Bit symbol WDTE WDTP1 (0300H) Read/Write R/W After reset 1 0 Function WDT Select detecting time 15 control 00 Enable 01 10 11: 2 Watchdog timer detection time SYSCR1 SYSCR1 ...
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WDCR Bit symbol (0301H) Read/Write After reset Read Function B1H: WDT disable code -modify 4EH: WDT clear code -write instructions are prohibited Figure 3.11.5 Watchdog Timer Control Register − W − B1H 4EH Others 91C016-170 ...
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Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared 0 by software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., ...
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Real Time Clock (RTC) 3.12.1 Function Description for RTC 1) Clock function (second, minute, hour, day, month, leap year) 2) Auto Calender function 12-hour (AM/PM) clock function ±30 second adjustment function (by software Alarm ...
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Control Registers Table 3.12.1 Page 0 (Timer function) Registers Symbol Address Bit7 Bit6 Bit5 SECR 0320H MINR 0321H 40 min 20 min 20 HOURR 0322H /PM/AM DAYR 0323H DATER 0324H Day 20 Day 10 MONTHR ...
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Detailed Explanation of Control Register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for Page 0 only Bit symbol SE6 SECR (0320H) Read/Write ...
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Minute column register (for Page 0/ MINR Bit symbol MI6 (0321H) Read/Write After reset Function min read. column ...
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Hour column register (for Page 0/ case of 24-hour clock mode (MONTHR<MO0> Page Bit symbol HOURR (0322H) Read/Write After reset Function 0 is read case of 12-hour clock mode ...
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Day of the week column register (for Page 0/ Bit symbol DAYR (0323H) Read/Write After reset Function (5) Day column register (for Page 0/ Bit symbol DATER (0324H) Read/Write After reset Function 0 is read. ...
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Month column register (for Page 0 only Bit symbol MONTHR (0325H) Read/Write After reset Function 0 is read. (7) Select 24-hour clock or 12-hour clock (for Page 1 only Bit symbol MONTHR (0325H) Read/Write After ...
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Year column register (for Page 0 only Bit symbol YE7 YE6 YEARR (0326H) Read/Write After reset Function 80 40 years years ...
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Page register setting (for Page 0/ Bit symbol INTENA PAGER (0327H) Read/Write R/W After reset 0 Read-modify Function Note: write Interrupt instruction 1: Enable are proibited 0: Disable Note: Pleas keep the setting order below and don’t ...
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Operational Description (1) Reading timer data a. There is the case which reads wrong data when carry of the inside counter happens during the operation which timer data reads. Therefore, please read two times with the following way for ...
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Timing of INTRTC and Clock data When time is read by interrupt, read clock data within 0.5s(s) after generating interrupt. This is because count up of clock data occurs by rising edge of 1Hz pulse cycle. ALARM INTRTC 1s ...
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Writing timer data When there is carry on the way of write operation, expecting data can not be wrote exactly. Therefore, in order to write in data exactly please follow the below way. a. Reset for a divider Inside ...
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Disabling the timer Carry of a timer is prohibited when write “0” to PAGER<ENATMR> and can prevent malfunction by 1s Carry hold circuit. During a timer prohibited, 1s Carry hold circuit holds one sec. carry signal which is generated ...
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Explanation of the Alarm Function Can use alarm function by setting of register of PAGE1 and output either of three signal from pin as follows by write “1” to PAGER<PAGE>. INTRTC outputs 1shot pulse ALARM when the falling edge ...
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LCD Driver Controller (LCDC) The TMP91C016 incorporates two types liquid crystal display driving circuit for controlling LCD driver LSI. One circuit handles a RAM build-in type LCD driver that can store display data in the LCD driver in itself, ...
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Feature of LCDC of Each Mode Each feature and operation of pin is as follows. Table 3.13.1 Feature of LCDC of Each Mode Shift- Register Type LCD Driver Common (Row): 64, 68, 80, 100, 120, The number of picture ...
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Block Diagram CPU address bus LCDSAH/L Lower address register (10 bits) Increment (14 bits) Internal data bus SCP System clock generate SEG CPU BUSAK SR,<BUS1:0> output counter (9 bits) Comparator SEG register Internal data bus To ...
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Control Registers 7 6 Bit symbol SAL15 SAL14 LCDSAL (0360H) Read/Write R/W R/W After reset 0 0 Function SR mode Display memory address (Low: A15 to A12 Bit symbol SAL23 SAL22 LCDSAH Read/Write R/W R/W (0361H) After ...
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Bit symbol FP7 FP6 LCDFFP Read/Write (0364H) After reset Function 7 6 − − Bit symbol LCDCTL2 (0366H) Read/Write R/W R/W After reset 0 0 Function Always write to 111 (Note) Note: Please write bit<7:5> to 111, even ...
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Register Address LCDC1L 0FE0H RAM built-in type column driver 1 LCDC1H 0FE1H LCDC2L 0FE2H RAM built-in type column driver 2 LCDC2H 0FE3H LCDC3L 0FE4H RAM built-in type column driver 3 LCDC3H 0FE5H LCDR1L 0FE6H RAM built-in type row driver LCDR1H ...
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Operation Explanation of Each Mode 3.13.4.1 Shift-register Type LCD Driver Control Mode (SR mode) Set the mode of operation, start address of source data save memory and LCD size to control registers before setting start register. After set start ...
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Settlement to frame frequency function TMP91C016 defines so-called frame period (Refresh interval for LCD panel) by the value set usually outputs the signal inverts polarity every frame period. Basic frame period; DLEBCD signal, is made according ...
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Timer out LCDCK LCD source clock (LCDCK) can select low frequency (XT1, XT2: 32.768 [kHz]) or timer out (TA3OUT) outputs from internal TMRA23. Example2: Here indicates the method that frame period is set 70 [Hz] by selecting TA3OUT for ...
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CLK A23 to A0 Normal CS signal LCLK mode (Only write) Note: When LCLK mode selected, CS signal out OR gate (Original CS signal and CS signal is not ouptut when read. Figure 3.13.5 LCLK Mode Timing Chart = 78.02 ...
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Table 3.13.2 Performance Listing for Each Segment and Common Number 64 68 com com XT number of counts for t LP 6.5 6.0 making 198.4 183 seg T STOP CPU stop rate 0.3 0.3 64 seg ...
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Table 3.13 6.5 6.0 5.0 COM COM + 0 78.77 80.31 81.92 COM + 1 77.56 79.15 80.91 COM 76.38 78.02 79.92 COM 75.24 76.92 78.96 COM 74.14 75.85 78.02 COM 73.06 74.81 77.10 COM ...
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Table 3.13 6.5 6.0 5.0 COM COM + 40 48.47 50.57 54.61 COM 48.01 50.10 54.16 COM 47.56 49.65 53.72 COM 47.11 49.20 53.28 COM 46.68 48.76 52.85 COM 46.25 48.33 52.43 COM 45.83 47.91 ...