FSCQ0565RT Fairchild Semiconductor, FSCQ0565RT Datasheet - Page 16

• Manufacturer Part Number: FSCQ0565RT
• Description: A Quasi-Resonant Converter (QRC) typically shows lower EMI and higher power conversion efficiency compared to conventional hard-switched converter with a fixed switching frequency
• Manufacturer: Fairchild Semiconductor

FSCQ-Series Rev. 1.1.2
reaches the second minimum level, as shown in Figure
10. Once the FSCQ-Series enters into the extended
quasi-resonant operation, the first sync signal is ignored.
After the first sync signal is applied, the sync threshold
levels are changed from 4.6V and 2.6V to 3V and 1.8V,
respectively, and the MOSFET turn-on time is synchro-
nized to the second sync signal. The FSCQ-Series
returns to its normal quasi-resonant operation when the
switching frequency reaches 45kHz as the load
increases.
3. Feedback Control: The FSCQ-Series employs cur-
rent mode control, as shown in Figure 11. An optocou-
pler (such as Fairchild’s H11A817A) and shunt regulator
(such as Fairchild’s KA431) are typically used to imple-
ment the feedback network. Comparing the feedback
voltage with the voltage across the Rsense resistor plus
an offset voltage makes it possible to control the switch-
ing duty cycle. When the reference pin voltage of the
KA431 exceeds the internal reference voltage of 2.5V,
the H11A817A LED current increases, pulling down the
feedback voltage and reducing the duty cycle. This event
typically happens when the input voltage is increased or
the output load is decreased.
3.1 Pulse-by-Pulse Current Limit: Because current
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of the PWM
comparator (Vfb*) as shown in Figure 11. The feedback
current (I
the maximum cathode voltage of diode D
which occurs when all I
resistors. Since D
(Vfb) exceeds 2.8V, the maximum voltage of the cathode
V
MOSFET Gate
V
ds
sync
2V
4.6V
2.6V
ON
Figure 10. Extended Quasi-Resonant
RO
FB
) and internal resistors are designed so that
Operation Waveforms
1
is blocked when the feedback voltage
FB
flows through the internal
ON
2
is about 2.8V,
3V
1.8V
16
of D2 is clamped at this voltage, thus clamping Vfb*.
Therefore, the peak value of the current through the
SenseFET is limited.
3.2 Leading Edge Blanking (LEB): At the instant the
internal Sense FET is turned on, there is usually a high
current spike through the Sense FET, caused by the
external resonant capacitor across the MOSFET and
secondary-side rectifier reverse recovery. Excessive volt-
age across the R
back operation in the current mode PWM control. To
counter this effect, the FSCQ-Series employs a leading
edge blanking (LEB) circuit. This circuit inhibits the PWM
comparator for a short time (T
is turned on.
4. Protection Circuits: The FSCQ-Series has several
self-protective functions such as over load protection
(OLP), abnormal over current protection (AOCP), over
voltage protection (OVP), and thermal shutdown (TSD).
OLP and OVP are auto-restart mode protections, while
TSD and AOCP are latch mode protections. Because
these protection circuits are fully integrated into the IC
without external components, the reliability can be
improved without increasing cost.
– Auto-restart mode protection: Once the fault condi-
V
o
tion is detected, switching is terminated and the
SenseFET remains off. This causes V
Vcc falls to the under voltage lockout (UVLO) stop volt-
age of 9V, the protection is reset and the FSCQ-Series
consumes only startup current (25µA). Then, the Vcc
capacitor is charged up, since the current supplied
through the startup resistor is larger than the current
that the FPS consumes. When V
voltage of 15V, the FSCQ-Series resumes its normal
operation. If the fault condition is not removed, the
SenseFET remains off and V
again. In this manner, the auto-restart can alternately
enable and disable the switching of the power
SenseFET until the fault condition is eliminated (see
Figure 12).
H11A817A
KA431
V
Modulation (PWM) Circuit
fb
Figure 11. Pulse Width
C
sense
B
4
I
delay
V
V
SD
resistor can lead to incorrect feed-
cc
D1 D2
V
V
ref
I
fb
FB
+
-
*
LEB
CC
2.5R
R
) after the Sense FET
OSC
drops to stop voltage
CC
OLP
reaches the start
CC
Driver
Gate
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to fall. When
R
sense
SenseFET