TLE 4473G V55-2 Infineon Technologies, TLE 4473G V55-2 Datasheet - Page 2

• Manufacturer Part Number: TLE 4473G V55-2
• Manufacturer: Infineon Technologies

Specifications of TLE 4473G V55-2

• Packages: PG-DSO-12
• Regulator Type: multiple output
• Output Voltage: 5V5V
• Accuracy: 2.5 %2.0 %
• Max. Output Current: 300mA190mA
• Dropout Voltage: 200mV

The device features a reset with adjustable power on delay for each of the outputs. In
addition the output for the microcontroller supply comes up with a watchdog in order to
supervise a connected microcontroller
Reset and Watchdog Behavior
The reset output RO2 is in high-state if the voltage on the delay capacitor
or equal
voltages greater than the reset threshold V
(‘reset condition’) a fast discharge of the delay capacitor
gets lower than
capacitor charge is the reset delay time. For the power-on case the charging process of
C
for the power-on reset delay time.
When the voltage on the delay capacitor has reached
watchdog circuit is enabled and discharges
If there is no rising edge observed at the watchdog input,
V
current
If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period
the periodical cycle starts again.
The watchdog timing is shown in
watchdog pulses corresponds to the minimum watchdog trigger time
capacitances on pin D2 result in longer watchdog trigger times:
If the output voltage Q1 decreases below
is discharged by the reset generator of the main output. If the voltage on this capacitor
drops below
above the reset threshold,
power-on-reset time the voltage on the capacitor reaches
be set high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of
Q1.
Data Sheet
t
T
D on
DL2
D2
WI,tr max
,
. Then reset output RO2 will be set to low and
starts from 0 V, which leads to the equation:
=
C
I
C
---------------------------- -
DC2
D2
V
D2
=
is charged again and the reset output stays high. After
DU2
I
until
0.34 ms/nF
DC2
V
. The delay capacitor
DL1
V
DU2
V
V
, a reset signal is generated on pin 2 (RO1). If the output voltage rises
DL2
D2
reaches
the reset output RO2 is set to low-level. The time for the delay
C
C
D2
D1
V
DU2
will be charged with the constant current
C
D1
and reset will be set high again.
Figure
using the above given equation (1) analogous for
C
D2
V
RT2
is charged with the current
2
RT1
C
1. The maximum duration between two
. If the output voltage gets lower than
D2
(typ. 4.65 V), the external capacitor
with the constant current
C
V
D2
DU2
C
will be charged again with the
C
V
D2
and reset was set to high, the
D2
DU1
sets in and as soon as
will be discharge down to
and the reset output will
V
D2
TLE 4473 GV55-2
Rev. 1.2, 2008-10-28
has reached
I
DC2
I
I
C
T
DC1
DD2
D2
WI,tr
for output
. After the
.
is greater
. Higher
V
V
DU2
C
V
RT2
(1)
(2)
D2
D1
,