MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet
MSC8101PG
Related parts for MSC8101PG
MSC8101PG Summary of contents
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... MSC8101 Programmer’s Quick Reference 16-Bit Digital Signal Processor MSC8101PG/D Revision 0, December 2000 ...
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StarCore, PowerQUICC II, OnCE, DigitalDNA, and the DigitalDNA logo are trademarks of Motorola, Inc. The PowerPC name is a trademark of international Business Machines Corporation used by Motorola under license from International Business Machines Corporation. Motorola reserves the right to ...
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MSC8101 Block Diagram Pins and External Signals MSC8101 Programmer’s Quick Reference Introduction Reset 4 Memory Maps 5 Registers 6 Interrupts 7 CPM 8 Instructions 9 iii ...
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Introduction 1 MSC8101 Block Diagram 2 Pins and External Signals 3 Reset 4 Memory Maps 5 Registers 6 Interrupts 7 CPM 8 Instructions 9 iv MSC8101 Programmer’s Quick Reference ...
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Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 2-1. MSC8101 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tables Table 1-1. MSC8101 and Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tables Table 8-2. Interfaces Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction This quick reference is designed to give programmers fast, easy access to summary information on key aspects of the MSC8101 device. It synthesizes and condenses information from multiple sources, including documentation on both the SC140 core and the ...
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MSC8101 Block Diagram CPM 3 x FCC UTOPIA 8 Interface 2 x MCC MII 4 x SCC { • SMC TDMs • • SPI Other Peripherals Extended Core Address Program Register Sequencer Address SC140 ...
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Pins and External Signals 3.1 Package Pinout D11 IRQ5 D10 IRQ1 D0 B IRQ3 THERM IRQ4 DP0 1 THERM IRQ2 IRQ6 D8 D ...
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Package Pinout D63 D62 D55 D51 D60 BADDR B DBG PWE6 D54 D50 D59 28 BADDR C DBB D61 D53 D49 D58 29 D BADDR GBL PWE5 D48 D57 D52 27 MOD PSD ...
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External Signals UTOPIA 8 TXENB/MII COL/PA31 UTOPIA 8 TXCLAV/TXCLAV0/RTS/MII CRS/PA30 UTOPIA 8 TXSOC/MII TX_ER/PA29 UTOPIA 8 RXENB/MII TX_EN/PA28 UTOPIA 8 RXSOC/MII RX_DV/PA27 UTOPIA 8 RXCLAV/RXCLAV0/MII RX_ER/PA26 UTOPIA 8 TXD0/MSNUM0/PA25 UTOPIA 8 TXD1/MSNUM1/PA24 UTOPIA 8 TXD4/TXD3 UTOPIA 8 TXD5/TXD2 UTOPIA ...
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External Signals Table 3-1. External Signals–SIU and Extended Core Data Name Direction A[0–31] Input/Output 60x Address Bus When the MSC8101 is in external master bus mode, these pins function as the 60x address bus. The MSC8101 drives the address of ...
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Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction ABB Input/Output 60x Address Bus Busy Output The MSC8101 asserts this pin for the duration of the address bus tenure. Following an address acknowledge (AACK) signal, which terminates the ...
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External Signals Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction D[48–51] Input/Output 60x Data Bus Bits 48–51 In write transactions the 60x bus master drives the valid data on this pin. In read transactions the 60x slave ...
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Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction D56 Input/Output 60x Data Bus Bit 56 In write transactions the 60x bus master drives the valid data on this pin. In read transactions the 60x slave drives the ...
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External Signals Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction IRQ1 Input Interrupt Request 1 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP1 Input/Output ...
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Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction IRQ5 Input Interrupt Request 5 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP5 Input/Output 60x Data ...
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External Signals Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction PSDVAL Input/Output 60x Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL is that the ...
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Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction PSDWE Output 60x Bus SDRAM Write Enable Output from the 60x bus SDRAM controller. This pin should connect to the SDRAM WE input signal. PGPL1 Output 60x Bus UPM ...
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External Signals Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction TDO Output Test Data Out (JTAG) Data output from the MSC8101 JTAG/COP controller. PORESET Input Power-On Reset When asserted, this input line causes the MSC8101 to enter ...
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Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction EE2 EOnCE Event 2 After PORESET is deasserted, you can configure EE2 as an input (default output. See the Emulation and Debug chapter in the SC140 DSP ...
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External Signals Table 3-1. External Signals–SIU and Extended Core (Continued) Data Name Direction Power Supply VDD The power supply of the internal logic. VDDH The power supply of the I/O Buffers. VCCSYN The power supply of the PLL circuitry. GNDSYN ...
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Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PA26 FCC1:UTOPIA 8 slave RxClav FCC1:UTOPIA 8 master RxClav FCC1:UTOPIA 8 master RxClav0 MPHY, direct polling FCC1:MII RX_ER PA25 FCC1:UTOPIA 8 TxD0 MSNUM0 PA24 FCC1:UTOPIA 8 TxD1 ...
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External Signals Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PA15 FCC1:UTOPIA 8 RxD5 FCC1:MII, HDLC nibble RxD2 PA14 FCC1:UTOPIA 8 RxD4 FCC1:MII, HDLC nibble RxD3 PA13 FCC1:UTOPIA 8 RxD3 MSNUM2 PA12 FCC1:UTOPIA 8 RxD2 ...
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Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PB29 FCC2:MII TX_EN TDM_B2:L1RSYNC PB28 FCC2:RTS FCC2:MII RX_ER SCC2:RTS, TENA TDM_B2:L1TSYNC/GRANT PB27 FCC2:MII COL TDM_C2:L1TXD PB26 FCC2:MII CRS TDM_C2:L1RXD PB25 FCC2:MII, HDLC nibble TxD3 TDM_A1:nibble L1TXD3 TDM_C2:L1TSYNC/GRANT ...
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External Signals Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PB21 FCC2:MII, HDLC nibble RxD0 FCC2:HDLC transparent RxD TDM_A1:nibble L1TXD2 TDM_D2:L1TSYNC/GRANT PB20 FCC2:MII, HDLC nibble RxD1 TDM_A1:nibble L1TXD1 TDM_D2:L1RSYNC PB19 FCC2:MII, HDLC nibble RxD2 I2C:SDA ...
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Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PC28 BRG4O CLK4/TIN1 Timer2:TOUT2 SCC2:CTS, CLSN PC27 BRG5O CLK5 Timer3/4:TGATE2 PC26 BRG6O CLK6 Timer3:TOUT3 TMCLK PC25 BRG7O CLK7/TIN4 DMA:DACK2 PC24 BRG8O CLK8/TIN3 Timer4:TOUT4 DMA:DREQ2 PC23 CLK9 DMA:DACK1 ...
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External Signals Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PC15 SMC2:SMTXD SCC1:CTS, CLSN FCC1:MPHY master TxAddr0 FCC1:MPHY slave TxAddr0 PC14 SI1:L1ST2 SCC1:CD, RENA FCC1:MPHY master RxAddr0 FCC1:MPHY slave RxAddr0 PC13 SI1:L1ST4 SCC2:CTS, CLSN FCC1:MPHY ...
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Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PC6 SI2:L1ST2 FCC1:CD FCC1:MPHY master RxAddr2 multiplexed polling FCC1:MPHY slave RxAddr2 multiplexed polling FCC1:MPHY master RxClav1 direct polling PC5 SMC1:SMTXD SI2:L1ST3 FCC2:CTS PC4 SMC1:SMRXD SI2:L1ST4 FCC2:CD PD31 ...
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External Signals Table 3-2. External Signals–CPM (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O PD19 FCC1:MPHY master TxAddr4 multiplexed polling FCC1:MPHY slave TxAddr4 multiplexed polling FCC1:MPHY master TxClav3 direct polling BRG1O SPI:SEL PD18 FCC1:MPHY master RxAddr4 multiplexed polling FCC1:MPHY ...
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Dedicated Pin Assignments by Port Table 3-3. Port A—Dedicated Pin Assignment (PPARA = 1) PSORA[ Pin PDIRA[ (Output) PA31 FCC1: TxEnb UTOPIA 8 master UTOPIA 8 slave PA30 FCC1: TxClav UTOPIA 8 slave UTOPIA 8 ...
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Dedicated Pin Assignments by Port Table 3-3. Port A—Dedicated Pin Assignment (PPARA = 1) (Continued) PSORA[ Pin PDIRA[ (Output) PA19 FCC1: TxD6 UTOPIA 8 FCC1: TxD1 MII/HDLC nibble PA18 FCC1: TxD7 UTOPIA 8 FCC1: TxD0 MII/HDLC ...
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Table 3-3. Port A—Dedicated Pin Assignment (PPARA = 1) (Continued) PSORA[ Pin PDIRA[ PDIRA[ (Output) PA8 SMC2: SMRXD PA7 SMC2: SMSYN PA6 Notes: 1. MSNUM[0–4] is the sub-block code of the peripheral controller using ...
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Dedicated Pin Assignments by Port Table 3-4. Port B Dedicated Pin Assignment (PPARB = 1) (Continued) PSORB[ Pin PDIRB[ (Output) PB23 FCC2: TxD1 TDM_A1: L1RXD2 MII/HDLC nibble PB22 FCC2: TxD0 TDM_A1: L1RXD1 MII/HDLC nibble FCC2: TxD ...
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Table 3-5. Port C Dedicated Pin Assignment (PPARC = 1) (Continued) PSORC[ PIN PDIRC[ PDIRC[ (Output) PC26 BRG6: BRGO PC25 BRG7: BRGO CLK7/TIN4 PC24 BRG8: BRGO CLK8/TIN3 PC23 PC22 SI1: L1ST1 Strobe PC15 SMC2: ...
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Dedicated Pin Assignments by Port Table 3-6. Port D Dedicated Pin Assignment (PPARD = 1) PSORD[ Pin PDIRD[ PDIRD[ (Output) PD31 PD30 SCC1: TXD PD29 SCC1: RTS SCC1: TENA Ethernet 1 PD19 FCC1: TxAddr4 ...
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Reset 4.1 Reset Causes Name Direction Power-on reset Input (PORESET) Hard reset (HRESET) I/O Soft reset (SRESET) I/O Software watchdog reset Bus monitor reset JTAG reset 4.2 Reset Actions for Each Reset Source Reset Logic Reset Source PLL and ...
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External Configuration Signals Pin RSTCONF Reset Configuration Input line sampled by the MSC8101 at the rising edge of PORESET. EE0 EONCE Event Bit 0 Input line sampled after core PLL locks. Holding EE[0] at logic 1 at the exit ...
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Bits Name 0 EARB External Arbitration 1 EXMC External MEMC 2 IRQ7 INT IRQ7 or INT_OUT Selection 3 EBM External PowerPC Bus Mode 4–5 BPS Boot Port Size 6 SCDIS SC140 Disabled 7 ISPS Internal Space Port Size 8–9 IRPC ...
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Host-Port Registers After Reset Register Name HCR HPCR HSR HCVR HORX HOTX Notes long dash (—) denotes bit value is indeterminate after reset. 2. “Empty” means that the data at this location is invalid (trash). Table 4-5. ...
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Table 4-6. Host-Side Registers After Reset Register Name Register Data ICR All bits CVR NMI HC HV[0–6] ISR HREQ HF[4–7] TRDY TXDE RXDF RX RX[0–3] TX TX[0–3] Notes long dash (—) denotes bit value is indeterminate after reset. ...
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Memory Maps Table 5-1. SC140 Core Internal Memory Map SC140 Core Internal Mnemonic Address 00000000–0007FFFF DSPRAM 00080000–00EFFDFF Reserved 00EFFE00–00EFFEFF EOnCE . SC140 Core Mnemonic Internal Address 0000 HCR 0020 HPCR 0040 HSR 0060 HCVR 0080 HOTX 00A0 HORX 0C00 ...
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Table 5-2. QBus Memory Map—Bank0 (Continued) SC140 Core Mnemonic Internal Address 1C00 ELIRA 1C08 ELIRB 1C10 ELIRC 1C18 ELIRD 1C20 ELIRE 1C28 ELIRF 1C30 IPRA 1C38 IPRB 1C48–FEFF Reserved FF00 QBUSMR0 FF02 QBUSBR0 FF04 QBUSMR1 FF06 QBUSBR1 FF08 QBUSMR2 FF0a ...
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Table 5-4. PowerPC Local Bus Memory Map PowerPC Local Bus Mnemonic Address 00000–7FFFF DSPRAM 0080 HOTX 00A0 HORX 0C00 FDIR 0C20 FDOR 0C20–FFFF Reserved Table 5-5. PowerPC 60x Bus Memory Map Internal Address Mnemonic 00000–03FFF DPRAM1 04000–07FFF Reserved 08000–08FFF DPRAM2 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 1002C PPC_ALRH 10030 PPC_ALRL 10034 LCL_ACR 10035 Reserved 10038 LCL_ALRH 1003C LCL_ALRL 10040 TESCR1 10044 TESCR2 10048 L_TESCR1 1004C L_TESCR2 10050 PDTEA 10054 PDTEM 10055 Reserved 10058 LDTEA 1005C ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 10114 OR2 10118 BR3 1011C OR3 10120 BR4 10124 OR4 10128 BR5 1012C OR5 10130 BR6 10134 OR6 10138 BR7 1013C OR7 10140 Reserved 10144 Reserved 10148 Reserved 1014C ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 10198 PURT 10199 Reserved 1019C PSRT 1019D Reserved 101A0 Reserved 101A4 Reserved 101A8 IMMR 101AC–101FF Reserved 10200–1021F Reserved 10220 TMCNTSC 10222 Reserved 10224 TMCNT 10228 Reserved 1022C TMCNTAL 10230–1023F ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 10720 DCHCR8 10724 DCHCR9 10728 DCHCR10 1072C DCHCR11 10730 DCHCR12 10734 DCHCR13 10738 DCHCR14 1073C DCHCR15 10740–1077F Reserved 10780 DIMR 10784 DSTR 10788 DTEAR 10789–1078B Reserved 1078C DPCR 1078D–1078F ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 10C40 SICR_EXT 10C42 Reserved 10C44 SIVEC_EXT 10C48 SIPNR_H_EXT 10C4C SIPNR_L_EXT 10C50 SIPRR_EXT 10C54 SCPRR_H_EXT CPM Interrupt Priority Register (high) 10C58 SCPRR_L_EXT 10C5C SIMR_H_EXT 10C60 SIMR_L_EXT 10C64 SIEXR_EXT 10C68–10C7F Reserved ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 10D30 PDATB 10D34–10D3F Reserved 10D40 PDIRC 10D44 PPARC 10D48 PSORC 10D4C PODRC 10D50 PDATC 10D54–10D5F Reserved 10D60 PDIRD 10D64 PPARD 10D68 PSORD 10D6C PODRD 10D70 PDATD 10D74–10D7F Reserved 10D80 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 10DA8 TCR3 10DAA TCR4 10DAC TCN3 10DAE TCN4 10DB0 TER1 10DB2 TER2 10DB4 TER3 10DB6 TER4 10DB8 Reserved 11018 SDSR 11019 Reserved 1101C SDMR 1101D Reserved 11020–112FF Reserved 11300 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 11320 GFMR2 11324 FPSMR2 11328 FTODR2 1132A Reserved 1132C FDSR2 1132E Reserved 11330 FCCE2 11334 FCCM2 11338 FCCS2 11339 Reserved 1133C FTIRR2_PHY0 1133D FTIRR2_PHY1 1133E FTIRR2_PHY2 1133F FTIRR2_PHY3 11340 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 11860 I2MOD 11862 Reserved 11864 I2ADD 11866 Reserved 11868 I2BRG 1186A Reserved 1186C I2COM 1186E Reserved 11870 I2CER 11872 Reserved 11874 I2CMR 11875–119BF Reserved 119C0 CPCR 119C4 RCCR 119C8 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 11A04 GSMR_H1 11A08 PSMR1 11A0A Reserved 11A0C TODR1 11A0E DSR1 11A10 SCCE1 11A12 Reserved 11A14 SCCM1 11A16 Reserved 11A17 SCCS1 11A18–11A1F Reserved 11A20 GSMR_L2 11A24 GSMR_H2 11A28 PSMR2 11A2A ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 11A50 SCCE3 11A52 Reserved 11A54 SCCM3 11A56 Reserved 11A57 SCCS3 11A58–11A5F Reserved 11A60 GSMR_L4 11A64 GSMR_H4 11A68 PSMR4 11A6A Reserved 11A6C TODR4 11A6E DSR4 11A70 SCCE4 11A72 Reserved 11A74 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 11A96 SMCE2 11A97 Reserved 11A9A SMCM2 11A9B–11A9F Reserved 11AA0 SPMODE 11AA2 Reserved 11AA6 SPIE 11AA7 Reserved 11AAA SPIM 11AAB Reserved 11AAD SPCOM 11AAE–11AFF Reserved 11B00 CMXSI1CR 11B01 Reserved 11B02 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 11B2A SI1CMDR 11B2B Reserved 11B2C SI1STR 11B2D Reserved 11B2E SI1RSR 11B30 MCCE1 11B32 Reserved 11B34 MCCM1 11B36 Reserved 11B38 MCCF1 11B39–11B3F Reserved 11B40 Reserved 11B42 SI2BMR 11B44 SI2CMR 11B46 ...
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Table 5-5. PowerPC 60x Bus Memory Map (Continued) Internal Address Mnemonic 12000–121FF SI1TxRAM 12200–123FF Reserved 12400–125FF SI1RxRAM 12600–127FF Reserved 12800–129FF SI2TxRAM 12A00–12BFF Reserved 12C00–12DFF SI2RxRAM 12E00–12FFF Reserved 13000–137FF Reserved 13800–13FFF Reserved 52 MSC8101 Programmer’s Quick Reference Name SI1 RAM SI1 ...
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Registers Convention Meaning R Read-only bit. Writing this bit has no effect. W Write-only bit. R/W Standard read/write bit. 6.1 Core Registers Mnemonic Register Name R[0–15] Address NSP, ESP Stack pointer Shadow stack pointer B[0–7] Base address N[0–3] Offset ...
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ADDRESS GENERATION UNIT (AGU R8/B0 R9/ R10/B2 R3 R11/B3 R12/ R13/B5 R14/ R15/B7 SP (NSP, ESP) Address Registers Base Address Offset and Registers Modifier Registers PROGRAM SEQUENCER UNIT (PSEQ) ...
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MCTL Modifier Control Register Bit AM[3–0] Bit AM[3–0] AM Mode Descriptions Linear addressing Reverse-carry addressing M0 used—Modulo addressing M1 used—Modulo addressing M2 used—Modulo addressing M3 used—Modulo addressing M0 used—Multiple wrap-around ...
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Bits Name 31 SLF Short Loop Flag 30 LF3 Loop Flag 3 29 LF2 Loop Flag 2 28 LF1 Loop Flag 1 27 LF0 Loop Flag 0 23–21 I[2–0] Interrupt Mask 20 OVE Overflow Exception Enable 19 DI Disable Interrupts ...
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S Scaling 5–4 S[1–0] Scaling Mode 3 RM Rounding Mode 2 SM Arithmetic Saturation Mode 1 T True 0 C Carry Table 6-3. Core Registers (Continued ...
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EMR Exception and Mode Register Bit — Type Reset Bit Type Reset Bits Name 23–17 GP[6-0] General Purpose Flags 16 BEM Big Endian Memory ...
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Extended Core Registers Bank Registers DSP Internal Name Description Address QBUSMR0 DSP Mask0 (option) 0x{Base0,FF00} Register QBUSBR0 DSP Base0 Address 0x{Base0,FF02} Register QBUSMR1 DSP Mask1 (option) 0x{Base0,FF04} Register QBUSBR1 DSP Base1 Address 0x{Base0,FF06} Register QBUSMR2 DSP Mask2 (option) 0x{Base0,FF08} ...
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Bits Name 0–3 HF[4–7] Host Flags 4 HICR ICR/HCR priority for DMA/Last Address Mode 5–7 HDM[0–2] Host DMA/Last Address Mode Control 5 RREQ (HICR = 1) RREQ Status 6–7 HM (HICR = 1) ICR[HM] Status 9 DBTE DMA Transmit Burst ...
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HCVR Host Command Vector Register Bit — Bits Name 8 HCP Host Command Pending 9–12 HV Host Vector HPCR Host Port Control Register Bit HAP HRP HCSP HDDS Bits Name 0 HAP ...
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HOTX Host Transmit Data Register A four 64-bit word FIFO. If HOTX is empty, writing it clears HSR[HTFE]. If HOTX contains three 64-bit words, writing it clears HTFNF. HORX Host Receive Data Register A four 64-bit word FIFO. If HORX ...
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TREQ/HDM0 HREQ/HTREQ Pin Control 15 RREQ/HDM0 HREQ and HRREQ Pin Control CVR Command Vector Register Bit — Bits Name 7 NMI Non-Maskable Interrupt 8 HC Host Command 9–15 HV Host Vector bits ISR Interface Status ...
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RXx Receive Word Registers [0–3] TXx Transmit Word Registers [0–3] RSCF Reset Configuration Registers [0–3] FCNT Filter Count Register Bit FCTL EFCOP Control Register Bit FDOM FDIM FONEIE FOFIE FINFIE Bits Name ...
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FOM Filter Operation Mode 12 FUPD Filter Update 13 FADP Filter Adaptive Mode 14 FLT Filter Type 15 FEN Filter Enable FACR EFCOP ALU Control Register Bit — Bits Name 8 FSCO Filter Shared Coefficients ...
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FDCH EFCOP Decimation/Channel Count Register Bit — Bits Name 4–7 FDCM Filter Decimation 10–15 FCHL Filter Channels FSTR EFCOP Status Register Bit Bits Name 9 FONBE Filter Data Output Buffer Not Empty ...
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ELIRC Edge/Level-Triggered Interrupt Priority Register C Bit PED11 PIL110 PIL111 PIL112 PED10 ELIRD Edge/Level-Triggered Interrupt Priority Register D Bit PED15 PIL150 PIL151 PIL152 PED14 ELIRE Edge/Level-Triggered Interrupt Priority Register E Bit 0 ...
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Bits Name 0–15 IP[15–0] Status of IR Inputs 15–0 IPRB Interrupt Pending Register B Bit IP31 IP30 IP29 IP28 Bits Name 0–7 IP[31–24] Status of NMI Inputs 31–24 8–15 IP[23–16] Status of IR Input 23–16 6.3 ...
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APD Address Phase Delay 8 PLDP Pipeline Maximum Depth 11 EAV Enable Address Visibility 12 ETM Compatibility Mode Enable 13 LETM Local Bus Compatibility Mode Enable 14 EPAR Even Parity 16–18 NPQM Non-MSC8101 Master Connected to Arbitration Lines 0 ...
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PRKM Parking Master PPC_ALRH PowerPC 60x Bus Arbitration-Level Register Bit Priority Field 0 Reset Bit Priority Field 4 Reset ...
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PRKM Parking Master LCL_ALRH PowerPC Local Bus Arbitration-Level Register Bit Priority Field 0 Reset Bit Priority Field 4 Reset ...
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PBSE Parity Byte Select Enable 3 IRQ7INT IRQ7 or INT_OUT selection 4–5 DPPC Data Parity Pins Configuration 6–7 IRPC Interrupt Pin Configuration (multiplexing) 10–11 TCPC Transfer Codes Pin Configuration 12–13 BC1PC Buffer Control 1-Pin Configuration 14-15 BCTLC Buffer Control ...
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Bits Name Description 0–14 ISB Internal Space Base 16–23 PARTNUM Part Number 24–31 MASKNUM Mask Number SYPCR System Protection Control Register Bit Reset Bit BMT ...
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TESCR1 PowerPC 60x Bus Transfer Error Status and Control Register 1 Bit ISBE PAR ECC2 ECC1 Bit — DMD Bits Name Description 0 BM PowerPC 60x Bus Monitor Time-Out ...
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L_TESCR1 Local Bus Transfer Error Status and Control Register 1 Bit — Bit — DMD TMCNTSC Time Counter Status and Control Register Bit — ...
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TMCNTAL Time Counter Alarm Register Bit Bit Bits Name Description 0–31 ALARM Alarm PISCR Periodic Interrupt Status and Control Register Bit — Bits Name Description ...
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PITR Periodic Interrupt Timer Register Bit Bit Bits Name 0–15 PIT Periodic Interrupt Timer RSR Reset Status Register Bit Reset Bit ...
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SICR/SICR_EXT SIU Interrupt Configuration Register Bit — Bits Name 2–7 HP Highest Priority 14 GSIU Group SIU (relative XSIU priority scheme) 15 SPS Spread Priority Scheme (relative YCC priority scheme) SIPRR/SIPRR_EXT SIU Interrupt Priority Register Bit ...
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SIPNR_H/SIPNR_H_EXT SIU High Interrupt Pending Register Bit — Bit — IRQ1 IRQ2 IRQ3 Notes: 1. These bits are zero after reset because their corresponding mask register bits are cleared (disabled). SIPNR_L/SIPNR_L_EXT SIU ...
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SIVEC/SIVEC_EXT SIU Interrupt Vector Register Bit Interrupt Code Bit SIEXR/SIEXR_EXT SIU External Interrupt Control Register Bit — EDPC4 EDPC5 EDPC6 EDPC7 Bit — EDI1 ...
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Bits Name 30–31 DFBRG Division Factor for the BRG Clock SCMR System Clock Mode Register Bit — COREPDF Bit SPLLPDF Bits Name 2–3 COREPDF Core PLL Pre-Division Factor 4–7 COREMF Core Multiplication ...
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BRx Base Registers [0–7, 10–11] Addr (BR0) 0x10100 (BR2) 0x10110 (BR1) 0x10108 (BR3) 0x10118 Bit Bit — PS Bits Name 0–16 BA Base Address 19–20 PS Port Size 21–22 DECC Data ...
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ORx Option Register—SDRAM Mode Addr (OR0) 0x10104 (OR2) 0x10114 (OR1) 0x1010C (OR3) 0x1011C Bit Bit LSDAM BPD Bits Name 0–11 SDAM SDRAM Address Mask 12–16 LSDAM Lower SDRAM Address Mask 17–18 BPD ...
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IBID Internal Bank Interleaving Within Same Device Disable ORx Option Register—GPCM Mode Addr (OR0) 0x10104 (OR2) 0x10114 (OR1) 0x1010C (OR3) 0x1011C Bit Reset Bit — BCTLD ...
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ORx Option Register—UPM Mode Addr (OR0) 0x10104 (OR2) 0x10114 (OR1) 0x1010C (OR3) 0x1011C Bit Bit — BCTLD Bits Name 0–16 AM Address Mask 19 BCTLD Data Buffer Control Disable 23 BI ...
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SDAM Address Multiplex Size 8–10 BSMA Bank Select Multiplexed Address Line 11–13 SDA10 “A10” Control 14–16 RFRC Refresh Recovery (recovery interval in clock cycles) 17–19 PRETOACT Precharge to Activate Interval (clock-cycle wait states) 20–22 ACTTORW Activate to Read/Write Interval ...
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MxMR Machine A/B/C Mode Registers Addr (MAMR) 0x10170 (MBMR) 0x10174 Bit BSEL RFEN OP Reset Bit RLFx WLFx Reset Bits Name 0 BSEL Bus ...
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GPL_x4DIS GPL_A4 Output Line Disable 14–15 RLFx Read Loop Field 18–21 WLFx Write Loop Field 22–25 TLFx Refresh Loop Field 26–31 MAD Machine Address MDR Memory Data Register Bit Bit MAR ...
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MPTPR Memory Refresh Timer Prescaler Register Bit PTP (Memory Timers Prescaler) Reset Notes: 1. Where x can be a zero or a one—that is, 0000_0010 or 0000_0011 DCHCRx DMA Channel Configuration Registers ...
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FLY Flyby Transaction 19–23 RQNUM Requestor Number 24 FRZ Freezes Channel 25 INT Internal Requestor 28–31 PRIO Channel Priority DPCR DMA Pin Configuration Register Bit 0 1 — Bit Name 4 SDN0 Select DONE[0] 5 SDN1 Select DONE[1] DSTR ...
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DEMR DMA External Mask Register Bit Bit DTEAR DMA Transfer Error Address Status Register Bit 0 1 DBER_P DBER_L Bits Name 0 DBER_P DMA Channel PowerPC 60x Bus ...
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DCPRAM DMA Channel Parameters RAM BDPTR Channel x Bits Name 0–31 BD_ADDR Buffer’s current address 32–63 BD_SIZE Size of transfer left for the current buffer BD_ATTR Buffer Attributes Parameter Bit INTRPT CYC CONT — NO_INC Bit ...
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Bits Name 0 INTRPT Interrupt 1 CYC Cyclic Address 2 CONT Continuous Buffer Mode 4 NO_INC Increments Address 5–6 BP Bus Priority (arbitrate for bus mastership) 9 NBUS Next Bus 10–15 NBD Next Buffer 22–24 TSZ Transfer Size (maximum transaction ...
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CPM, Parallel I/O Ports To/from internal bus From DED OUT1 0 1 From DED OUT2 PSOR To DED IN1 PPAR and PSOR and PDIR 0 To DED IN2 PPAR and PSOR and PDIR Port Register Name PDATx PDIRx PPARx ...
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PDATx Port Data Registers [A–D] Addr (PDATA) 0x10D10 (PDATB) 0x10D30 Bit Bit D16 D17 D18 D19 Notes: 1. These bits are valid for PDATA ...
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Bits Name 0–31 DDx Dedicated Enable PSORx Port Special Options Registers [A–D] Addr (PSORA) 0x10D08 (PSORB) 0x10D28 Bit SO0 SO1 SO2 SO3 Bit SO16 SO17 SO18 SO19 Notes: ...
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Interrupts 7.1 Interrupt Structure External IRQ[2–3] SDMA + CPM Peripherals Port C External IRQ[1,4–7] HOST SC140 Core Figure 7-1. MSC8101 Interrupt Flow Diagram MSC8101 Programmer’s Quick Reference SIC_EXT SIU SIC SIC Pins DMA EFCOP EOnCE PIC Interrupt Structure INT_OUT ...
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Interrupt Priorities and Vector Tables 7.2 Interrupt Priorities and Vector Tables Table 7-1. SIC and SIC_EXT Interrupt Source Priority Priority Level (Highest to Lowest ...
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Table 7-1. SIC and SIC_EXT Interrupt Source Priority (Continued) Priority Level (Highest to Lowest ...
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Interrupt Priorities and Vector Tables Table 7-1. SIC and SIC_EXT Interrupt Source Priority (Continued) Priority Level (Highest to Lowest Table 7-2. SIC and SIC_EXT Interrupt Vectors Interrupt ...
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Table 7-2. SIC and SIC_EXT Interrupt Vectors (Continued) Interrupt Number 27– 46– ...
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Interrupt Priorities and Vector Tables Table 7-2. SIC and SIC_EXT Interrupt Vectors (Continued) Interrupt Number 60–63 VAB[0–5] Signal 0x0 TRAP Internal exception (generated by trap instruction) 0x1 — 0x2 ILLEGAL 0x3 DEBUG 0x4 — 0x5 OVERFLOW 0x6 ...
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Table 7-3. PIC Interrupt Vectors (Continued) VAB[0–5] Signal 0x30 IRQ16 0x31 IRQ17 External IRQ3 (edge/level configurable) 0x32 IRQ18 DMA interrupt (channel/buffer terminated) 0x33 IRQ19 0x34 IRQ20 EOnCE interrupt (edge-triggered) 0x35 IRQ21 0x36 IRQ22 0x37 IRQ23 0x38 NMI0 0x39 NMI1 0x3A ...
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Protocols Supported 8 CPM 8.1 Protocols Supported Table 8-1. MSC8101 Protocols Supported versus Channels Protocol FCC1 FCC2 FCC3 ATM (Utopia 8) + ATM (serial) + Ethernet (100BaseT) + Ethernet (10BaseT) + HDLC + HDLC_BUS TRANSPARENT + UART Multi channel HDLC ...
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Interfaces Supported Communication Controllers 8.3 Serial Performance FCC1 FCC2 155 Mbps ATM 100 BaseT 100BaseT 100 BaseT 155 Mbps ATM 100BaseT 100 BaseT 128 * 64-Kbps channels 155 Mbps ATM 100BaseT 45 Mbps HDLC 45 Mbps HDLC 100 BaseT ...
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Parameter RAM Values 8.4 Parameter RAM Values Page 12–16 Notes: 1. Offset from RAM_BASE 106 MSC8101 Programmer’s Quick Reference Table 8-4. Parameter RAM 1 Address Peripheral 0x8000 SCC1 0x8100 ...
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CP Command Operation Codes (Opcodes) CPCR CP Command Register Bit RST PAGE Bit — Bits Name 0 RST Software Reset Command 1–5 PAGE Page Number Table 8-5. CP Command Register . ...
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SBC Sub-Block Code Sub- Code Block FCC1 10000 (for ATM: 01110) FCC2 10001 (for ATM: 01110) FCC3 10010 SCC1 00100 SCC2 00101 SCC3 00110 SCC4 00111 SMC1 01000 SMC2 01001 RAND 01110 15 FLG Command Semaphore Flag 18–25 MCN ...
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Table 8-6. CP Command Operation Codes (Opcodes) Opcode FCC SCC (UART/Transparent) 0000 init rx and init rx and init rx and tx params tx params tx params 0001 init rx params init rx init rx params params 0010 init tx ...
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Instructions Section 9.1, SC140 Instruction Type Grouping Rules, and Section 9.2, Conventions, Syntax, Abbreviations, provide general information about the MSC8101 instructions and how this guide represents them. Section 9.3, Instructions Grouped Alphabetically, contains details about the instructions. 9.1 SC140 ...
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Table 9-1. Instruction Conventions (Continued) Convention Db Single source data register De Even numbered data/core register Dn Destination data register Do Odd numbered data/core register DR Data or address register Ea Effective address HP High portion (bits [31–16 ...
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Table 9-2. Operations Syntax (Continued) Operator Logical AND Logical OR Exclusive OR Bitwise complement Test for equality equal not equal Transfer left to right Either right or left transfers, but not both at once Arithmetic right ...
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Table 9-3. Assembler Syntax (Continued) Operator label Replace the word “label” instruction with the label name of an execution set in code. The instruction determines if the assembler substitutes an absolute address or a relative displacement in the ...
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Instructions Grouped Alphabetically Mnemomic Operation ABS Absolute value Dn Dn ADC Add long with carry ADD Add # ADD2 Add two 16-bit values Da.H + Dn.H ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation ADR Add and round Rnd(Da + Dn) Dn AND Bitwise AND #$000000u16 Da Dn #u16$0000 AND Bitwise AND with 16-bit operand #u16 DR.L DR.L #u16 DR.L DR.L ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation ASLL Multi-bit arithmetic shift left Dn # Da[6:0] 0, then Dn Da[6:0] else Dn |Da[6:0]| ASLW Word arithmetic shift left (16 bit shift) Da<<16 Dn ASR Arithmetic shift right by ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation BMCHG Bit-mask change a 16-bit operand ~C1.H C1.H (i denotes bits=1 in #u16 ~C1.L C1 ~DR.H DR ~DR.L DR BMCHG.W Bit-mask change a 16-bit ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation BMSET Bit-mask set a 16-bit operand 1 C1.H (i denotes bits=1 in #u16 C1 DR DR.L i BMTSET Bit-mask test and set a 16-bit operand 1 ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation BMTSTC.W Bit-mask test a 16-bit operand in memory if clear if (#u16 & (SP – u5)) == $0000, then 1 else (#u16 & (SP + s16)) == $0000, then ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation BREAK Terminate the loop and branch to an address PC + displacement PC 0 LFn BSR Branch to subroutine (Next PC) (SP); SR ( displacement ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation CMPEQ.W Compare for equal If # Dn, then 1 T, else 0 If #s16 = = Dn, then 1 T, else 0 CMPEQA Compare for equal Rx, ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation CONTD Jump to the start of the loop to start the next iteration (delayed) (LC >1: 3 cycles cycles.) If LCn 1, then SAn PC else PC + displacement ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation DIV Divide iteration If Dn[39] Da[39 then (Da & $FF FFFF 0000) else – (Da & $FF FFFF 0000) ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation EOR Bitwise Exclusive 16-bit operand #u16 DR.L DR.L #u16 DR.H DR.H EOR.W Bitwise Exclusive 16-bit operand in memory #u16 (R) (R) #u16 (SP – u5) SP ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation IFc Execute current execution set or subgroup unconditionally then execute set/subgroup else treat as NOP then execute set/subgroup else treat as NOP execute set/subgroup ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation IMPYHLUU Multiply unsigned integer and unsigned integer; first source from high portion, second from low portion Da.H * Db.L Dn IMPYSU Multiply signed integer and unsigned integer Da.H * Db.L Dn IMPYUU ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation JFD Jump if false (delayed) (4 cycles minus time for delay slot, but not less than 1 cycle) If T==0, then label PC If T==0, then Rn PC JMP Jump label PC ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation LSLL Multi-bit bitwise shift left If Da[6:0] > 0, then Dn << Da[6:0] else Dn >>> Da[6:0] LSR Bitwise shift right by one bit (Dn>>>1) Dn; 0 Dn[39] LSRA Bitwise shift right ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MACUU Multiply-accumulate unsigned fraction and unsigned fraction Dn + (Da.L * Db.L) Dn MARK Push the PC into the trace buffer PC trace buffer MAX Transfer maximum signed value If Da > ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVE.2F Move two fractional words from memory to a register pair SIGN (EA) OPERAND EXTENSION Db SIGN (EA+2) OPERAND EXTENSION (EA) Da:Db Notes: 1. Add one cycle when EA ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVE.4F Move four fractional words from memory to a register quad SIGN (EA) EXTENSION Db SIGN (EA+2) EXTENSION Dc SIGN (EA+4) EXTENSION Dd SIGN (EA+6) EXTENSION (EA) Da:Db:Dc:Dd Notes: ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVE.B Move byte to/from memory 31 SIGN EXTENSION 39 SIGN EXTENSION (aa (aa) (Rn + s15) DR (ea) DR (SP + s15) DR Notes: 1. Add one cycle when EA ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVE.L Move long word SIGN EXTENSION #s32 C4 #u32 MOVE.L Move long register extensions EXTENSION La + EXTENSION Lb Note: ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVE.L Move long SIGN EXTENSION (aa) DR (aa) C4 (Rn + u3) DR (Rn + s15) DR (Rn + Rr) DR (EA) DR (Rn) C3 (SP–u6) DR (SP+s15) ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVE.W Move integer word to/from memory, or immediate to register or memory 31 SIGN EXTENSION 39 D SIGN EXTENSION #s7 DR #s16 C4 #s16 (aa) #s16 (SP–u5) #s16 (Rn) #s16 (SP+sa16) Description ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVE.W Move immediate integer word (sign extended for memory reads) 31 SIGN EXTENSION 39 D SIGN EXTENSION (aa) DR (aa) C4 (Rn + u3) DR (Rn + s15) DR (Rn + Rr) ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVES.4F Move four fractional words to memory with scaling and saturation Da:Db:Dc:Dd (EA) Notes: 1. Add one cycle when EA = (Rn + N0). MOVES.F Move fractional word to memory with saturation ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MOVEU.L Move unsigned long from memory ZERO EXTENSION #u32 Db MOVEU.W Move unsigned integer word from memory UNCHANGED 39 Db UNCHANGED #u16 Db[31:16] #u16 Db[15:0] MOVEU.W ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation MPYR Multiply signed fractions and round Rnd((Da.H * Db.H)) Dn MPYSU Multiply signed fraction and unsigned fraction Da.H * Db.L Dn MPYUS Multiply unsigned fraction and signed fraction Da.L * Db.H Dn ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation OR Bitwise 16-bit operand #u16 DR.L DR.L #u16 DR.H DR.H OR.W Bitwise 16-bit operand in memory #u16 R (R) #u16 (SP – u5) SP – u5) ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation POPN Pop a register from the software stack using the normal stack pointer EXTENSION La + EXTENSION Lb (NSP – 8) De; NSP – 8 NSP (NSP – ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation PUSHN Push a register onto the software stack using the normal stack pointer EXTENSION La + EXTENSION Lb De (NSP); NSP + 8 NSP Do (NSP + 4); ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation RTED Return from exception (delayed) (Shadow SP valid: 5 cycles. Not valid: 6 cycles.) (SP – (SP – – NMID RTS Return from subroutine ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation SAT.F Saturate fractional value in data register to fit in high portion If Da > $007FFFFFFF then $007FFF0000 If Da < $FF80000000 then $FF80000000 Else Da & $FFFFFF0000 Dn SAT.L Saturate value ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation SUBA Subtract (affected by the modifier mode) Rx – # – SUBL Shift left and subtract (2 * Dn) – SUBNC.W Subtract without changing the carry ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation TRAP Execute a software exception (Cycle count depends upon machine state.) PC (ESP), SR (ESP + 4), ESP + 8 VBR[31:12]:trap_vector PC TSTEQ Test for equal to zero then ...
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Table 9-5. Instructions Grouped Alphabetically (Continued) Mnemomic Operation VSL Viterbi shift left: specialized move to support Viterbi kernel If VF2 == 1, then (D3 else (D1 VF0 == 1, then (D3.L 1) else ...
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Instructions Grouped Alphabetically 148 MSC8101 Programmer’s Quick Reference ...
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Index Numerics 60x Address Acknowledge (AACK) signal 7 60x Address Bus (A[0-31]) signal 6 60x Address Bus Busy (ABB) signal 7 60x Address Retry (ARTRY) signal 7 60x Bus Arbiter Configuration Register 69 60x Bus Arbitration-Level Register 70 60x Bus ...
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Clock Mode 1-3 (MODCK[1-3]) signals 14 Clock Out (CLKOUT) signal 16 Clocks memory map 43 Command Vector Register 63 Communications processor (CP) memory map 47 Communications processor module (CPM) command set, opcodes 109 CPM, parallel I/O ports 94 interfaces supported ...
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H H8BIT (H8BIT) signal 9 Hard Reset (HRESET) signal 14 Hard Reset Configuration Word 32 HCR Register 59 HCVR Register 61 HORX Register 62 Host Acknowledge (HACK) signal 9 Host Address Line 0-3 HA[0-3] signals 8 Host Chip Select (HCS) ...
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SDRAM Mode 83 UPM Mode 85 ORx-GPCM Mode 84 ORx-SDRAM Mode 83 ORx-UPM Mode 85 P parallel I/O port registers 94 Parameter RAM Values 106 PDATx Registers 95 PDIRx Registers 95 Periodic Interrupt Status and Control Register 76 Periodic Interrupt ...
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System Clock Control Register 80 System Clock Mode Register 81 System integration timers memory map 41 System interface unit (SIU) interrupt controller memory map 42 PIC interrupt vectors 102 SIC and SIC_EXT interrupt source priority 98 SIC and SIC_EXT interrupt ...
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MSC8101 Programmer’s Quick Reference ...