MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 92

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

ORx
21–22 ACS
24–27 SCY
30–31 EHTR
0–16 AM
Reset
Reset
Bits
Addr
27
19
20
28
29
Bit
Bit
IBID
BCTLD
CSNT
SETA
TRLX
AM
16
0
1
0
(OR1) 0x1010C
Name
(OR0) 0x10104
Option Register—GPCM Mode
17
1
1
0
—
Internal Bank Interleaving Within Same Device Disable
Address Mask
Data Buffer Control Disable
Chip-Select Negation Time
Address to Chip-Select Setup
(CS output /address change)
Cycle Length in Clocks
External Access Termination
Timing Relaxed
Extended Hold Time on Read Accesses
(clock cycles inserted)
18
2
1
0
BCTLD
19
3
1
0
(OR3) 0x1011C
(OR2) 0x10114
CSNT
Description
20
4
1
1
Table 6-12. Memory Controller Registers (Continued)
21
5
1
1
ORx—GPCM Mode Bit Descriptions
ACS
22
6
1
1
(OR5) 0x1012C
(OR4) 0x10124
23
—
7
0
0
AM
0 = Enabled
0 = Corresponding bits masked
0 = BCTLx asserted.
0 = CS/WE negated normally
1 = CS/WE negated a quarter of a clock earlier
00 = Same time
01 = Reserved
0000 = 0 wait states
0 = PSDVAL generated internally by the memory controller unless GTA is
1 = PSDVAL generated after external logic asserts GTA
0 = Normal
00 = 0
24
8
0
1
asserted earlier externally.
25
9
0
1
(OR7) 0x1013C
(OR6) 0x10134
SCY
01 = 1
10
26
0
1
…
11
27
0
1
Settings
1 = Corresponding address bits used
1 = BCTLx not asserted
10 = CS output 1/4 clock after
11 = CS output 1/2 clock after
1111 = 15 wait states
1 = Relaxed
10 = 4
1 = Disabled
SETA
12
28
0
0
Type: R/W
(OR11) 0x1015C
(OR10) 0x10154
TRLX
13
29
0
1
11 = 8
14
30
0
0
EHTR
15
31
0
0