MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 64

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

23–21 I[2–0]
11–8 VF[3–0]
Bits
31
30
29
28
27
20
19
18
SLF
LF3
LF2
LF1
LF0
OVE
DI
EXP
Name
Short Loop Flag
Loop Flag 3
Loop Flag 2
Loop Flag 1
Loop Flag 0
Interrupt Mask
Overflow Exception Enable
Disable Interrupts
Exception Mode
Viterbi Flags
Description
Table 6-3. Core Registers (Continued)
SR Bit Descriptions
0 = Active loop length is three or more execution sets
1 = Active loop length is one or two execution sets
0 = Hardware loop #4 not enabled
0 = Hardware loop #3 not enabled
0 = Hardware loop #2 not enabled
0 = Hardware loop #1 not enabled
0 = Overflow exception generation is disabled
1 = Overflow exception generation is enabled, unless EMR[DOVF] bit = 1
0 = Interrupts enabled
0 = Normal processing mode, active stack pointer is NSP
1 = Exception processing mode, active stack pointer is ESP
0 = Appropriate 16-bit portion transferred
1 = Appropriate 16-bit portion not transferred
Notes:
I2
0
0
0
0
1
1
1
1
1. An IPL0 exception is always masked.
I1
0
0
1
1
0
0
1
1
I0
0
1
0
1
0
1
0
1
Settings
1 = Hardware loop #4 enabled
1 = Hardware loop #3 enabled
1 = Hardware loop #2 enabled
1 = Hardware loop #1 enabled
1 = Interrupts disabled
Exceptions
Permitted
IPL[1–7]
IPL[2–7]
IPL[3–7]
IPL[4–7]
IPL[5–7]
IPL[6–7]
IPL7
NMI
Exceptions
Masked
IPL[0–1]
IPL[0–2]
IPL[0–3]
IPL[0–4]
IPL[0–5]
IPL[0–6]
IPL[0–7]
IPL0