MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 71

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MSC8101PG

Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
CVR
ISR
9–15 HV
9–12 HF[4–7]
Bits
Bits
14
15
13
14
15
7
8
8
Bit
Bit
TREQ/HDM0
RREQ/HDM0
NMI
HC
HREQ
TRDY
TXDE
RXDF
0
0
Name
Name
Command Vector Register
Interface Status Register
1
1
HREQ/HTREQ Pin Control
HREQ and HRREQ Pin Control
Non-Maskable Interrupt
Host Command
Host Vector bits
HREQ Status
Host flags 4
TRDY Status
Transmit Data Empty
Receive Data Full
2
2
7
3
3
Description
Description
4
4
Table 6-5. HDI16 Registers (Continued)
5
5
CVR Bit Descriptions
ISR Bit Descriptions
6
6
Reset: Depends on reset configuration sequence
Reset: Depends on reset configuration sequence
NMI
7
7
TREQ when written; HDM0 when read
RREQ when written; HDM0 when read
HDRQ cleared:
0 = No host processor interrupts requested
1 = Interrupt requested
HDRQ set:
0 = No host processor interrupts requested (HTRQ or HRRQ cleared)
1 = Interrupt requested (HTRQ or HRRQ set)
Reflect state of HCR[HF] bits
1 = TTX[0–3] and the HORX FIFO are not empty
0 = TX registers are not empty
1 = TX registers are empty and can be written by the host processor
0 = RX registers are not full
1 = RX registers are full and can be read by the host processor
0 = TX[0
HREQ
HC
8
8
3] and the HORX FIFO are empty
HF4
9
9
HF5
10
10
HF6
11
11
Settings
Settings
HF7
HV
12
12
Type: R/W
Type: R
TRDY
13
13
TXDE
14
14
RXDF
15
15
0x1
0x2

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