MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 14

• Manufacturer Part Number: MSC8101PG
• Description: MSC8101PG 16-Bit Digital Signal Processor Quick Reference
• Manufacturer: Motorola / Freescale Semiconductor

External Signals
6
BADDR[29–31]
IRQ[2–3,5]
TSIZ[0–3]
A[0–31]
TT[0–4]
Name
TBST
IRQ1
GBL
NC
BR
BG
Input/Output 60x Address Bus
Input/Output 60x Bus Transfer Type
Input/Output 60x Transfer Size
Input/Output 60x Bus Transfer Burst
Input/Output
Input/Output
Input/Output
Direction
Output
Output
Output
Input
Input
Input
Input
Data
Table 3-1. External Signals–SIU and Extended Core
When the MSC8101 is in external master bus mode, these pins function as the 60x
address bus. The MSC8101 drives the address of its internal 60x bus masters and
responds to addresses generated by external 60x bus masters. When the MSC8101 is
in Internal Master Bus mode, these pins are used as address lines connected to
memory devices and are controlled by the MSC8101 memory controller.
The 60x bus master drives these pins during the address tenure to specify the type of
transaction.
The 60x bus master drives these pins with a value indicating the number of bytes
transferred in the current transaction.
The 60x bus master asserts this pin to indicate that the current transaction is a burst
transaction (transfers four quad words).
Interrupt Request 1
One of eight external lines that can request a service routine, via the internal interrupt
controller, from the SC140 core.
Global
When a 60x master within the chip initiates a bus transaction, it drives this pin. When an
external 60x master initiates a bus transaction, it should drive this pin. Assertion of this
pin indicates that the transfer is global and it should be snooped by caches in the
system.
The primary (general-purpose) signal is a no connect (NC).
Burst Addresses 29–31
Outputs of the 60x memory controller. These pins are used in external master
configuration. They connect directly to memory devices controlled by the MSC8101
memory controller.
Interrupt Requests 2–3, 5
External lines that can request a service routine, via the internal interrupt controller, from
the SC140 core.
60x Bus Request
An output when an external arbiter is used. The MSC8101 asserts this pin to request
ownership of the 60x bus.
An input when an internal arbiter is used. An external master should assert this pin to
request 60x bus ownership from the internal arbiter.
60x Bus Grant
An output when an internal arbiter is used. The MSC8101 asserts this pin to grant 60x
bus ownership to an external PowerPC bus master.
An input when an external arbiter is used. The external arbiter should assert this pin to
grant 60x bus ownership to the MSC8101.
MSC8101 Programmer’s Quick Reference
Description