MSC8101PG Motorola / Freescale Semiconductor, MSC8101PG Datasheet - Page 80

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MSC8101PG

Manufacturer Part Number
MSC8101PG
Description
MSC8101PG 16-Bit Digital Signal Processor Quick Reference
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
IMMR
10–11 TCPC
12–13 BC1PC
16–17 MMR
14-15 BCTLC
4–5
6–7
Type
Type
2
3
Bit
Bit
PBSE
IRQ7INT
DPPC
IRPC
16
0
Internal Memory Map Register
17
1
Parity Byte Select Enable
IRQ7 or INT_OUT selection
Data Parity Pins Configuration
Interrupt Pin Configuration (multiplexing)
Transfer Codes Pin Configuration
Buffer Control 1-Pin Configuration
Buffer Control Configuration
Mask Master’s Requests
18
2
19
PARTNUM
3
20
4
Table 6-8. SIU Registers (Continued)
21
5
Reset: Depends on reset configuration sequence
22
6
ISB
23
7
R/W
R
0 = Disabled
0 = IRQ7
00 = NC, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6
01 = DP0, DP1, DP2, DP3, DP4, DP5, DP6
10 = NC, IRQ1, NC, NC, DREQ3, DREQ4, DACK3
11 = EXT_BR2, EXT_BG2, EXT_DBG2, EXT_BR3, EXT_BG3,
00 = NC, NC, NC
01 = IRQ2, IRQ3, IRQ5
10 = BADDR29, BADDR30, BADDR31
11 = Reserved
00 = TC0, TC1, TC2
01 = reserved
10 = BNKSEL0, BNKSEL1, BNKSEL2
11 = reserved
00 = BCTL1
00 = BCTL0 controls W/R. BCTL1 controls OE.
01 = BCTL0 controls W/R. BCTL1 controls OE.
10 = BCTL0 controls WE. BCTL1 controls RE.
11 = reserved
00 = No masking on bus request lines
01 = Reserved
10 = Reserved
11 = All external bus requests masked (boot master is the internal core)
24
8
EXT_DBG3, IRQ6
25
9
01 = BCTL1
10
26
11
27
MASKNUM
1 = Enabled
1 = INT_OUT
10 = reserved
12
28
13
29
11 = reserved
14
30
0x101A8
15
31

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