FST16211MEAX Fairchild Semiconductor, FST16211MEAX Datasheet

no-image

FST16211MEAX

Manufacturer Part Number
FST16211MEAX
Description
24-Bit Bus Switch
Manufacturer
Fairchild Semiconductor
Datasheet
© 2000 Fairchild Semiconductor Corporation
FST16211GX
(Note 1)
FST16211MEA
FST16211MTD
FST16211
24-Bit Bus Switch
General Description
The Fairchild Switch FST16211 provides 24-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organized as a 12-bit or 24-bit bus switch.
When OE
nected to Port 1B. When OE
to Port 2B. When OE
exists between the A and B Ports.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: BGA package available in Tape and Reel only.
Logic Diagram
Order Number
1
is LOW, the switch is ON and Port 1A is con-
Package Number
1/2
Preliminary
BGA54A
is HIGH, a high impedance state
MS56A
MTD56
2
is LOW, Port 2A is connected
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
[TAPE and REEL]
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500037
Features
4 switch connection between two ports
Minimal propagation delay through the switch
Low l
Zero bounce in flow-through mode
Control inputs compatible with TTL level
Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
CC
Package Description
July 1997
Revised August 2000
www.fairchildsemi.com

Related parts for FST16211MEAX

FST16211MEAX Summary of contents

Page 1

... Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1: BGA package available in Tape and Reel only. Logic Diagram © 2000 Fairchild Semiconductor Corporation Features 4 switch connection between two ports Minimal propagation delay through the switch ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA TOP VIEW www.fairchildsemi.com Pin Descriptions Pin Name Description Bus Switch Enables 1 2 1A, 2A Bus A 1B, 2B Bus B FBGA Pin Assignments 1 ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Switch Voltage (V ) (Note Input Voltage (V ) (Note Input Diode Current ( Output (I ) Sink Current ...

Page 4

AC Electrical Characteristics Symbol Parameter t ,t Prop Delay Bus to Bus (Note 8) PHL PLH Output Enable Time PZH PZL Output Disable Time PHZ PLZ Note 8: This parameter is guaranteed by design ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide Package Number BGA54A Preliminary 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS56A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 ...

Page 8

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE ...

Related keywords