HM-65162 Intersil Corporation, HM-65162 Datasheet - Page 7

• Manufacturer Part Number: HM-65162
• Description: 2kx8 Asynchronous Cmos Static Ram
• Manufacturer: Intersil Corporation

Timing Waveforms
In this write cycle G has control of the output after a period,
TGHQZ. G switching the output to a high impedance state
allows data in to be applied without bus contention after
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention; within
2. On RAMs which have selects or output enables (e.g., S, G), one
VCC -0.3V to VCC +0.3V.
of the selects or output enables should be held in the deselected
V
CC
E
ADDRESS
(Continued)
W
G
Q
E
D
4.5V
TGHQZ
FIGURE 4. DATA RETENTION TIMING
(12) TAVWL
(17) TDVWH
FIGURE 3. WRITE CYCLE II
(15)
HM-65162/883
V
(22) TAVWH
CC
RETENTION
V
-0.3V TO V
CC
(10) TAVAX
TIMING
DATA
(11) TELWH
≥ 02.0V
194
(13) TWLWH
(21) TDVEH
TGHQZ. When W transitions high, the data in can change
after TWHDX to complete the write cycle.
3. Inputs which are to be held high (e.g., E) must be kept between
4. The RAM can begin operation > 55ns after VCC reaches the min-
CC
state to keep the RAM outputs high impedance, minimizing
power dissipation.
VCC +0.3V and 70% of VCC during the power up and down tran-
sitions.
imum operating voltage (4.5V).
+0.3V
TWHAX
(14)
4.5V
>55ns
(18) TWHDX