DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet
DSP56721
Related parts for DSP56721
DSP56721 Summary of contents
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... MHz clock. The DSP56720/DSP56721 are high density CMOS devices with 3.3 V inputs and outputs. The DSP56720 device is slightly different than the DSP56721 device—the DSP56720 includes an external memory interface while the DSP56721 device does not. The ...
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... Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .4 1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6 1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7 1.4 Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.2 Thermal Characteristics .10 2.1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . .10 2.1.4 DC Electrical Characteristics . . . . . . . . . . . . . . .11 2.1.5 AC Electrical Characteristics . . . . . . . . . . . . . . .12 2 ...
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... Figure 1. DSP56720 Block Diagram EXTAL/XTAL CGM ASRC Arbiter 8 Shared Bus 0 Shared Bus 1 Arbiters 0–7 Shared Memory 8K Blocks 0–7 (64K total) 2 JTAGs JTAG Figure 2. DSP56721 Block Diagram DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 DSP Core-1 On-Chip Memory PCU OnCE / AGU DMA / ALU ...
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... Pin Assignments DSP56720 devices are available in one package type; DSP56721 devices are available in two package types. For the pin assignments of a specific device in a specific package, please see sections 1.2–1.1. Device DSP56720 DSP56721 For more detailed information about signals, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM). ...
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... IO_GND 30 PLLP1_GND 31 PLLP1_VDD 32 PLLD1_GND 33 PLLD1_VDD 34 PLLA1_GND 35 PLLA1_VDD 36 Figure 3. DSP56720 144-Pin Package Pinout TM Symphony Freescale Semiconductor DSP56720 144-Pin DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 108 IO_GND 107 IO_VDD 106 WDT 105 PINIT/NMI 104 TDO 103 TDI 102 TCK 101 TMS 100 SDO2_1/SDI3_1 99 ...
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... Pinout for DSP56721 80-Pin Plastic LQFP Package For the pinout of the DSP56721 80-pin plastic LQFP package, see SDO2_3/SDI3_3 1 SDO3_3/SDI2_3 2 SDO4_3/SDI1_3 3 SDO5_3/SDI0_3 4 IO_VDD 5 IO_GND 6 CORE_VDD 7 CORE_GND 8 SPDIFIN1/SDO2_2/SDI3_2 9 SPDIFOUT1/SDO3_2/SDI2_2 10 SDO4_2/SDI1_2 11 SDO5_2/SDI0_2 12 FSR_3 13 SCKR_3 14 SCKT_3 15 GND 16 GND 17 GND 18 GND 19 GND 20 TM Symphony 6 Figure 4. DSP56721 80-Pin Figure 4 ...
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... GND 33 GND 34 GND 35 GND 36 Figure 5. DSP56721 144-Pin Package Pinout 1.4 Pin Multiplexing Many pins are multiplexed. For more about pin multiplexing, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM). TM Symphony Freescale Semiconductor Figure 5. DSP56721 144-Pin DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 108 IO_GND 107 ...
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... Table 3. Chip-Level Conditions For Ratings” Characteristics” Requirements” Characteristics” Characteristics” Clocks” Operation” CAUTION NOTE DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 See on page 8 on page 17 See on page 8 on page 10 on page 10 on page 11 on page 12 on page 12 on page 13 Timing” ...
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... PLLP_VDD, V IO_VDD PLLA_VDD and GND I I lsync_out I lclk I ale I JTAG STG — — DSP56720 / DSP56721 Multi-Core Audio Processors, Rev Value Unit -0 1. GND -0 ° -40 to +125 C ° -65 to +150 ...
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... To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins. Figure 6. Prevent High Current Conditions by Using External Schottky Diode If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead ...
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... DDIO — — -10 TSI V 2 -16 mA, TDO V — mA, TDO R — — PD DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 1.0V Typ Max Unit 1.0 1.1 V 3.3 3.46 V — IO_VDD+2V — 0.8 V μA — ± — pF μA — 10 — — V — ...
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... The timing waveforms shown in the AC electrical characteristics section are tested with a V minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are measured with the production test machine V 2 ...
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... External Clock Operation The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in EXTAL XTAL R XTAL1 C If the DSP56720/DSP56721 system clock is an externally supplied square wave voltage source connected to EXTAL (Figure 10) ...
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... Minimum edge-triggered interrupt request assertion width 17 Minimum edge-triggered interrupt request deassertion width 18 Delay from interrupt trigger to interrupt code execution TM Symphony 14 Table 8. Clock Operation Symbol 1 Eth Etl Etc Tc Table 9. 3 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Min Max Units 16.67 100 ns 2.5 inf 16.67 100 ns 2.5 inf 5 inf ns 33.3 500 5 ...
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... RESET duration” conditions (as specified above) have not been yet met, the device circuitry will uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. TM Symphony Freescale Semiconductor DD DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Expression Min Max (128K × T 655 — × ...
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... IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 b) General Purpose I/O General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 Figure 12. External Fast Interrupt Timing Diagram TM Symphony Reset Value Figure 11. Reset Timing Diagram DSP56720 / DSP56721 Multi-Core Audio Processors, Rev Freescale Semiconductor ...
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... Table 10. Module-Level Specifications For 2 C Protocol 2 C Serial Clock” Timing” Timing” Timing” Timing” Timing” Timing” only)” DSP56720 / DSP56721 Multi-Core Audio Processors, Rev IRQA, IRQB, IL IRQC,IRQD, NMI See Timing” on page 18 Timing” ...
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... Very Narrow Narrow Wide Master Bypassed Very Narrow Narrow Wide Slave Bypassed Very Narrow Narrow Wide Master — Slave — DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 16, Figure 17, and Figure 18 for timing diagrams. Expression Min Max 59.0 — 59.0 — ...
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... Narrow Wide Slave — 2 Slave — Master Bypassed /Slave Very Narrow Narrow Wide Master Bypassed /Slave Very Narrow Narrow Wide Slave — DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Expression Min Max Unit T +15 25 — 2 2 — ns — 0 — ...
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... Very Narrow Narrow Wide Slave — Slave — Master Bypassed Very Narrow 0 Narrow Wide Master — Master — Master — pF. L DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Expression Min Max 3 — — — ...
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... SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 29 MISO (Input) MOSI (Output) 40 HREQ (Input) Figure 15. SPI Master Timing Diagram (CPHA = 0) TM Symphony Freescale Semiconductor MSB Valid 33 MSB 42 43 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev LSB Valid 34 LSB 21 ...
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... SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 40 HREQ (Input) Figure 16. SPI Master Timing Diagram (CPHA = 1) TM Symphony MSB Valid 33 MSB DSP56720 / DSP56721 Multi-Core Audio Processors, Rev LSB Valid 34 LSB Freescale Semiconductor ...
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... SCK (CPOL = 1) (Input) 31 MISO (Output) 29 MOSI (Input) HREQ (Output) Figure 17. SPI Slave Timing Diagram (CPHA = 0) TM Symphony Freescale Semiconductor MSB 30 MSB Valid 36 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev LSB 29 30 LSB Valid 38 23 ...
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... C Protocol Timing Figure 19 for the timing diagram Protocol Timing Parameters 2 Standard I C Symbol/ 1,2,3,4,5 Expression — F SCL T SCL T BUF T SUSTA DSP56720 / DSP56721 Multi-Core Audio Processors, Rev LSB 29 30 LSB Valid 37 36 Standard Fast-Mode Unit Min Max Min Max — ...
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... C × × × 130 C T AS;RQI t HO;RQI = -40°C to 125° pF DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Standard Fast-Mode Unit Min Max Min Max μs 4.0 — 0.6 — μs 4.7 — 1.3 — μs 4.0 — 1.3 — — 5.0 — ...
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... SCL serial clock cycle ( CCP (Nominal, SCL Serial Clock Cycle (TSCL) generated as master MSB Figure 19 Timing Diagram DSP56720 / DSP56721 Multi-Core Audio Processors, Rev LSB ACK Stop Freescale Semiconductor Eqn. 1 Eqn. 2 Eqn SCL Eqn. 4 ...
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... DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Figure 23 for timing diagrams. 5 Min Max Condition 4 × 20.0 — × 20.0 — × — — ...
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... Symbol Expression 6 — 6 — — — — — — 7 — — 6 — — — — — — DSP56720 / DSP56721 Multi-Core Audio Processors, Rev Min Max Condition — — 20 — 10 — — 22 — 12 — — 19 — ...
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... Periodically sampled and not 100% tested. 8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI. TM Symphony Freescale Semiconductor Symbol — — — = -40°C to 125° pF. L DSP56720 / DSP56721 Multi-Core Audio Processors, Rev Expression Min Max Condition — — C — — 18.0 — ...
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... In normal mode, the output flag state is asserted for the entire frame period. Figure 20. ESAI Transmitter Timing Diagram TM Symphony First Bit DSP56720 / DSP56721 Multi-Core Audio Processors, Rev Last Bit 88 91 See Note Freescale Semiconductor ...
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... Out Data In FSR (Bit) In FSR (Word) In Flags In HCKT SCKT (Output) TM Symphony Freescale Semiconductor First Bit Figure 21. ESAI Receiver Timing Diagram 95 96 Figure 22. ESAI HCKT Timing Diagram DSP56720 / DSP56721 Multi-Core Audio Processors, Rev Last Bit ...
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... Table 14. Timer Timing Parameters Expression 2 × × -40°C to 125° Figure 25 Table 15. GPIO Timing Parameters 1 Characteristics DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Unit Min Max + 2.0 12.0 — 2.0 12.0 — for the timing diagram. Expression Min Max — ...
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... 102 103 Valid 104 106 Figure 25. GPIO Timing Diagram Figure Table 16. JTAG Timing Parameters Characteristics × 3); maximum 10 MHz) C DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Expression Min Max — — — 13.0 — — 13.0 100 101 ...
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... V M VIH VIL 111 Figure 26. Test Clock Input Timing Diagram 112 114 Output Data Valid 115 114 Output Data Valid Figure 27. Debugger Port Timing Diagram DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 All Frequencies Unit Min Max 5.0 — ns 25.0 — ns — 44.0 ns — ...
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... Delay from timer clear to rise of WDT, WDT_1 2.2.9 Host Data Interface (HDI24) Timing The HDI24 module is only on the DSP56721 device; the DSP56720 device does not have a HDI24 module. Also, only 16 bits of the HDI24 interface are pinned out on the DSP56721 device. See Figure ...
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... A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W hold time after data strobe deassertion 8 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read Symphony 36 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 200 MHz Expression Unit Min Max — 13.2 — ...
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... The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 10. In this calculation, the host request signal is pulled 4.7 kW resistor in the open-drain mode. 11. HDI24_1 specs match those of HDI24. TM Symphony Freescale Semiconductor = 50 pF. L DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 200 MHz Expression Unit Min Max 2 × T 10.0 — ...
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... HD23 HOREQ, HRRQ, HTRQ Figure 30. HDI24 Read Timing Diagram, Non-Multiplexed Bus TM Symphony 38 317 327 326 336 337 330 317 328 332 327 326 340 341 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 318 328 329 333 318 319 329 338 Freescale Semiconductor ...
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... HA0 HWR, HDS HD0 HOREQ, Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus TM Symphony Freescale Semiconductor – HA2 336 331 HCS 320 324 – HD23 340 341 HRRQ, HTRQ DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 337 333 321 325 339 39 ...
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... HAD0 HAD23 HOREQ, HRRQ, HTRQ Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus TM Symphony 40 336 322 HAS 323 317 334 335 327 329 Address 326 340 341 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 337 318 319 328 Data 338 Freescale Semiconductor ...
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... Figure 34. HDI24 Host DMA Write Timing Diagram TM Symphony Freescale Semiconductor 336 322 323 320 334 335 Address 340 341 342 343 344 320 321 TXH/M/L Write 324 325 Data Valid DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 324 321 325 Data 339 41 ...
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... Valid (Output) Table 19. S/PDIF Timing Parameters Symbol — — — — — — — srckp srckph srckpl stclkp stclkph stclkpl DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 342 328 329 Figure 36 and Figure 37 for timing All Frequency Unit Min Max — 0.7 ns — 1.5 ns — ...
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... SRCK ) (Output STCLK (Input) 2.2.11 EMC Timing (DSP56720 only) The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see Table 21, and Table 22; for timing diagrams, see Table 20. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV Parameter LCLK cycle time ...
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... Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV Symphony 44 T clk_skew T sync_in_skew T T asynchronous input T asynchronous input upwait T T out_s out_h ad_s ad_h T T ale_h ale DSP56720 / DSP56721 Multi-Core Audio Processors, Rev clk in_s T in_h gta ad_z Freescale Semiconductor ...
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... Notes negative hold time means that the signal could be invalid before the LCLK rising edge. TM Symphony Freescale Semiconductor Symbol DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Min Max T 20 — clk T 8 — in_s T -1 — in_h ...
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... T ad_s ad_h T T ale_h ale Symbol T clk T in_s 1 T in_h T gta T upwait T ale_h T ale T out_s T out_h DSP56720 / DSP56721 Multi-Core Audio Processors, Rev clk T in_h Min Max Unit 40 — — — — — — — ...
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... Freescale Semiconductor Symbol T ad_s T ad_h T ad_z T T asynchronous input T asynchronous input upwait T T out_s out_h ad_s ad_h T T ale_h ale DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Min Max Unit 18 – 17 – – clk in_s T in_h gta ad_z ...
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... See the DSP56720 Reference Manual (DSP56720RM) for detailed functional and applications information. 4 Hardware Design Considerations For design considerations, also see Section 2.1.3, “Power 5 Ordering Information Table 23 provides ordering information for both the DSP56720 and DSP56721. Product DSP56720 DSP56721 6 Package Information For the outline drawings of available device packages, see Device ...
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... Figure 41. 80-Pin Package Outline Drawing ( Symphony Freescale Semiconductor DSP56720 / DSP56721 Multi-Core Audio Processors, Rev ...
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... Figure 42. 80-Pin Package Outline Drawing ( Symphony 50 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Freescale Semiconductor ...
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... Package Outline Drawing For the 144-pin package drawings, see figures Figure 43. 144-Pin Package Outline Drawing ( Symphony Freescale Semiconductor Figure 43 and Figure 44. DSP56720 / DSP56721 Multi-Core Audio Processors, Rev ...
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... Figure 44. 144-Pin Package Outline Drawing ( Symphony 52 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Freescale Semiconductor ...
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... DSP56300 Family Manual (document number DSP56300FM). Detailed description of the 56300-family architecture and the 24-bit core processor and instruction set. DSP56720/DSP56721 Reference Manual (document number DSP56720RM). Detailed description of memory, peripherals, and interfaces. DSP56720 Product Brief (DSP56720PB). Brief description of the DSP56720 device. ...
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... TM Symphony 54 DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3 Freescale Semiconductor ...
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... TM Symphony Freescale Semiconductor DSP56720 / DSP56721 Multi-Core Audio Processors, Rev ...
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