DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 15

• Manufacturer Part Number: DSP56721
• Description: Dsp56721 Multi-core Audio Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Notes:
No.
19
20
21
22
1.
2.
3.
4.
Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)
Interrupt Requests Rate
DMA Requests Rate
When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast
interrupts. Long interrupts are recommended when using Level-sensitive mode.
For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by
the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get
locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 μs.
Periodically sampled and not 100% tested.
RESET duration is measured during the time in which RESET is asserted, V
V
be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the
shortest possible duration.
• PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0)
• PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 =
• PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 =
• PLL is not active during Stop and Stop delay is not enabled (OMR Bit
• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
• Timer, Timer_1
• IRQ, NMI (edge trigger)
DD
1)
0)
6 = 1)
general-purpose transfer output valid caused by first interrupt
instruction execution
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry will
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
Symphony
1, 2, 3
1
1
TM
Characteristics
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
DD
is valid, and the EXTAL input is active and valid. When
(25 x T
(128K x T
10 x T
Expression
(128K × T
25 × T
12 x T
12 x T
T
8 x T
8 x T
6 x T
7 x T
2 x T
3 x T
C
LOCK
) + T
C
+ 3.8
C
C
C
C
C
C
C
C
C
C
LOCK
C)
) +
Min
655
125
855
200
—
—
—
—
—
—
—
—
—
Max
53.8
60.0
40.0
40.0
60.0
30.0
35.0
10.0
15.0
—
—
—
—
Unit
μs
ns
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
15