DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 29

• Manufacturer Part Number: DSP56721
• Description: Dsp56721 Multi-core Audio Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Notes:
No.
95
96
97
1.
2.
3.
4.
5.
6.
7.
8.
HCKR/HCKT clock cycle
HCKT input rising edge to SCKT output
HCKR input rising edge to SCKR output
V
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(Asynchronous implies that SCKT and SCKR are two different clocks.)
i ck s = internal clock, synchronous mode
(Synchronous implies that SCKT and SCKR are the same clock.)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal
waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit
clock of the first word in frame.
Periodically sampled and not 100% tested.
ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
CORE_VDD
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
= 1.00 ± 0.10 V; T
Characteristics
Symphony
TM
J
= -40°C to 125°C; C
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
1, 3, 4
L
= 50 pF.
Symbol
—
—
—
Expression
2 x T
—
—
C
5
Min
10
—
—
Max
18.0
18.0
—
Condition
—
—
—
2
Unit
ns
ns
ns
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