DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 18

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DSP56721

Manufacturer Part Number
DSP56721
Description
Dsp56721 Multi-core Audio Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
2.2.1
See
18
No.
XX Tolerable Spike width on data or clock in
23
24
25
26
Table 11
Minimum serial clock cycle = t
Serial clock high period
Serial clock low period
Serial clock rise/fall time
for SHI SPI protocol timing parameters and
Serial Host Interface (SHI) SPI Protocol Timing
Characteristics
Symphony
Table 11. Serial Host Interface SPI Protocol Timing Parameters
1,3,4
TM
SPICC
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
(min)
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Figure
15,
Very Narrow
Very Narrow
Very Narrow
Very Narrow
Very Narrow
Very Narrow
Very Narrow
Filter Mode
Figure
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Narrow
Narrow
Narrow
Narrow
Narrow
Narrow
Narrow
Wide
Wide
Wide
Wide
Wide
Wide
Wide
16,
Figure
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
2.0 x T
10 x T
10 x T
0.5 x (t
0.5 x (t
0.5 x (t
0.5 x (t
0.5 x (t
0.5 x (t
0.5 x (t
0.5 x (t
Expression
10 x T
10 x T
17, and
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SPICC
SPICC
SPICC
SPICC
SPICC
SPICC
SPICC
C
C
+ 186.6
+ 186.6
+ 186.6
SPICC
+ 133
+ 333
+ 19.6
+ 19.6
+ 86.6
+ 19.6
+ 19.6
+ 86.6
+ 19.6
+ 19.6
+ 86.6
+ 9
+ 9
Figure 18
)
)
)
)
)
)
)
Freescale Semiconductor
183.0
373.0
193.2
393.2
186.5
196.6
186.5
196.6
59.0
59.0
59.2
59.2
29.5
29.5
91.5
29.6
29.6
96.6
29.5
29.5
91.5
29.6
29.6
96.6
Min
for timing diagrams.
Max
100
10
50
0
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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