DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 26

• Manufacturer Part Number: DSP56721
• Description: Dsp56721 Multi-core Audio Processor
• Manufacturer: Freescale Semiconductor, Inc

2.2.3
The programmed serial clock cycle, T
control register).
The expression for T
where
In I
to
The programmed serial clock cycle (T
shown in Equation 4.
26
2
C mode, the user may select a value for the programmed serial clock cycle from
— HRS is the pre scaler rate select bit. When HRS is cleared, the fixed
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be
T
HREQ
I
2
CCP
SDA
SCL
divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed.
selected.
Programming the SHI I
+ 3 × T
Stop
I
2
45
CCP
Symphony
C
46
is
47
60
+ 45ns + T
Start
T
I
2
CCP
50
4096 × T
TM
= [T
6 × T
I
I
2
2
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
CCP
CCP
R
C
49
× 2 × (HDM[7:0] + 1) × (7 × (1 — HRS) + 1)]
C
, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock
) should be chosen in order to achieve the desired SCL serial clock cycle (T
C
61
Figure 19. I
44
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
(if HDM[7:0] = $02 and HRS = 1)
MSB
(if HDM[7:0] = $FF and HRS = 0)
52
2
C Serial Clock
58
2
51
C Timing Diagram
48
57
55
53
LSB
ACK
59
56
Freescale Semiconductor
Stop
SCL
Eqn. 1
Eqn. 2
Eqn. 3
Eqn. 4
), as