DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 43

• Manufacturer Part Number: DSP56721
• Description: Dsp56721 Multi-core Audio Processor
• Manufacturer: Freescale Semiconductor, Inc

2.2.11
The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see
Table
Freescale Semiconductor
LCLK cycle time
LCLK skew to LSYNC_OUT
Input setup to LSYNC_IN (except LGTA/LUPWAIT)
Input hold from LSYNC_IN (except LGTA/LUPWAIT)
LGTA valid time
LUPWAIT valid time
LALE negedge to LAD(address phase) invaild (address latch
hold time)
LALE valid time
Output setup from LSYNC_IN (except LAD[23:0] and LALE)
Output hold from LSYNC_IN (except LAD[23:0] and LALE)
LAD[23:0] output setup from LSYNC_IN
LAD[23:0] output hold from LSYNC_IN
LSYNC_IN to output high impedance for LAD[23:0]
21, and
(Output
STCLK
(Input)
SRCK
Table
)
EMC Timing (DSP56720 only)
Table 20. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)
22; for timing diagrams, see
Symphony
Parameter
TM
Figure 37. S/PIDF STCLK Timing Diagram
Figure 36. S/PDIF SRCK Timing Diagram
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
Figure
stclkpl
srckpl
V
V
M
M
38,
Figure
stclkp
srckp
39, and
T
Symbol
T
clk_skew
T
T
T
T
T
T
T
T
upwait
T
T
T
ale_h
out_s
out_h
ad_h
ad_s
ad_z
in_s
in_h
gta
ale
clk
Figure
stclkph
srckph
V
V
M
M
40.
Min
3.8
3.5
1.5
10
—
12
12
—
2
2
3
4
2
Max
160
4.3
—
—
—
—
—
—
—
—
—
—
—
Table
Unit
20,
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43