GS1560A Gennum Corporation, GS1560A Datasheet
GS1560A
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GS1560A Summary of contents
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... Loop-Through Cable Driver DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION The GS1560A is a reclocking deserializer with a serial loop- through cable driver. When used in conjunction with the GS1524 Automatic Cable Equalizer and the GO1525 Voltage Controlled Oscillator, a receive solution can be realized for HD-SDI, SD-SDI and DVB-ASI applications. ...
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... DVB-ASI word alignment and 8b/10b decode HOST Interface / JTAG Reset test GS1560A FUNCTIONAL BLOCK DIAGRAM GS1560A FUNCTIONAL BLOCK DIAGRAM GS1560A FUNCTIONAL BLOCK DIAGRAM GS1560A FUNCTIONAL BLOCK DIAGRAM DATA_ERROR CRC correct CRC check Line mumber Line mumber correct DOUT[19:0] check ...
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... Automatic Video Standard and Data Format Detection ............................................ 38 3.10.5 Error Detection and Indication.............................................................................. 41 3.10.6 Error Correction and Insertion ............................................................................. 45 3.10.7 EDH Flag Detection ............................................................................................ 47 3.11 Parallel Data Outputs ........................................................................................................ 48 3.11.1 Parallel Data Bus Buffers .................................................................................... 48 3.11.2 Parallel Output in SMPTE Mode ............................................................................ 48 3.11.3 Parallel Output in DVB-ASI Mode .......................................................................... 48 3.11.4 Parallel Output in Data-Through Mode ................................................................... 48 GENNUM CORPORATION 27360-1 ...
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... Configuration and Status Registers ....................................................................... 51 3.13 JTAG .............................................................................................................................. 51 3.14 Device Power Up .............................................................................................................. 51 4. APPLICATION REFERENCE DESIGN .................................................................................................... 52 4.1 Typical Application Circuit (Part A) ......................................................................................... 52 4.2 Typical Application Circuit (Part B) ......................................................................................... 53 5. REFERENCES & RELEVANT STANDARDS ............................................................................................. 54 6. PACKAGE & ORDERING INFORMATION................................................................................................ 54 6.1 Package Dimensions ........................................................................................................... 54 6.2 Ordering Information ........................................................................................................... 55 7. REVISION HISTORY........................................................................................................... 55 GENNUM CORPORATION 27360-1 ...
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... CD2 14 DDI_2 15 TERM2 16 DDI_2 17 SMPTE_BYPASS 18 19 RSET CD_VDD GENNUM CORPORATION GS1560A (Top View IO_GND 59 DOUT17 58 DOUT16 DOUT15 57 56 DOUT14 55 DOUT13 54 DOUT12 53 IO_VDD ...
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... Analog 7 TERM1 Analog 9 DVB_ASI Non Synchronous 10 IP_SEL Non Synchronous GENNUM CORPORATION TYPE - Power Power supply connection for the charge pump. Connect to +3.3V DC analog. - Power Ground connection for the phase detector and serial digital input buffers. Connect to analog GND. - Power Power supply connection for the phase detector. Connect to +1.8V DC analog ...
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... Non Synchronous 13 IOPROC_EN/DIS Non Synchronous GENNUM CORPORATION TYPE DESCRIPTION Input / CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Output Signal levels are LVCMOS/LVTTL compatible. This pin will be an input set by the application layer in slave mode, and will be an output set by the device in master mode. ...
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... CD_VDD 21 SDO_EN/DIS Non Synchronous 22 CD_GND GENNUM CORPORATION TYPE Input STATUS SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of a serial digital input signal. Normally generated by a Gennum automatic cable equalizer. When LOW, the serial digital input signal received at the DDI2 and DDI2 pins is considered valid ...
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... JTAG/HOST Non Synchronous 27 CS_TMS Synchronous with SCLK_TCK GENNUM CORPORATION TYPE DESCRIPTION Output Serial digital loop-through output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or 270Mb/s. The slew rate of these outputs is automatically controlled to meet SMPTE 292M and 259M specifications according to the setting of the SD/HD pin. Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible ...
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... SCLK_TCK 30 SCLK_TCK Non Synchronous 31 DATA_ERROR Synchronous with PCLK GENNUM CORPORATION TYPE DESCRIPTION Output CONTROL SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Output / Test Data Output Host Mode (JTAG/HOST = LOW) SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device ...
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... V Synchronous with PCLK 36 H Synchronous with PCLK 37, 64 CORE_VDD GENNUM CORPORATION TYPE Output CONTROL SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used as a control signal for external FIFO(s). Normally HIGH but will go LOW for one PCLK period at SAV. - Power Ground connection for the digital core logic. Connect to digital GND. ...
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... PIN NAME TIMING NUMBER 38, 39, DOUT[0:9] Synchronous 42–48, 50 with PCLK 40, 49, 60 IO_GND 41, 53, 61 IO_VDD GENNUM CORPORATION TYPE Output PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. HD 20-bit mode SD/HD = LOW 20bit/10 bit = HIGH HD 10-bit mode SD/HD = LOW 20bit/10 bit = LOW SD 20-bit mode SD/HD = HIGH ...
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... PIN DESCRIPTIONS (CONTINUED) PIN NAME TIMING NUMBER 51, 52, DOUT[10:19] Synchronous 54–59, 62, with PCLK 63 GENNUM CORPORATION TYPE DESCRIPTION Output PARALLEL DATA BUS Signal levels are LVCMOS/LVTTL compatible. HD 20-bit mode Luma data output in SMPTE mode SD/HD = LOW SMPTE_BYPASS = HIGH 20bit/10 bit = HIGH DVB_ASI = LOW ...
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... Synchronous with PCLK 67 FW_EN/DIS Non Synchronous 69 PCLK GENNUM CORPORATION TYPE Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the presence of ancillary data in the video stream. HD Mode (SD/HD = LOW) The YANC signal will be HIGH when the device has detected VANC or HANC data in the luma video stream and LOW otherwise ...
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... Signal levels are LVCMOS/LVTTL compatible. Used to determine the input / output selection for the DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS pins. When set HIGH, the GS1560A is set to operate in master mode where DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become status signal output pins set by the device. In this mode, the GS1560A will automatically detect, reclock, deserialize and process SD SMPTE, HD SMPTE, or DVB-ASI input data ...
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... CP_CAP Analog 79 LB_CONT Analog 80 CP_GND GENNUM CORPORATION TYPE Input Differential inputs for the external VCO reference signal. For single ended devices such as the GO1525, VCO should be AC coupled to VCO_GND. VCO is nominally 1.485GHz. - Power Ground reference for the external voltage controlled oscillator. Connect to pins and 8 of the GSO1525 ...
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... Ambient Operating Temperature Storage Temperature Lead Temperature (soldering, 10 sec) NOTES: 1. See reflow profile solder Temperature 230˚C 220˚C 183˚C 150˚C 100˚C 25˚C GENNUM CORPORATION VALUE/UNITS -0.3V to +2.1V -0.3V to +4.6V -2. 5.25V -20°C < T < 85°C A -40°C < T < 125°C STG 230°C 3˚ ...
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... Production test at room temperature and nominal supply voltage sample test. 5. Calculated result based on Level Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. GENNUM CORPORATION CONDITIONS MIN TYP System 0 -25 1.65 1 ...
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... Serial Input Data Rate DR DDI ∆ V Serial Digital Input Signal DDI Swing Serial Output Data Rate DR SDO Serial Output RiseTime tr SDO 20% ~ 80% Serial Output Fall Time tf SDO 20% ~ 80% GENNUM CORPORATION CONDITIONS MIN TYP System Nominal loop 0.6 - bandwidth No data DVB-ASI - - ...
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... Production test at room temperature and nominal supply voltage sample test. 5. Calculated result based on Level Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. GENNUM CORPORATION CONDITIONS MIN TYP Pseudorandom and - 90 pathological HD signal ...
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... DDI Fig. 2 Serial Digital Input VCO VDD 25 1. VCO Fig. 4 VCO Input 8K 800mV Fig. 6 PLL Loop Bandwidth Control GENNUM CORPORATION Fig. 5 VCO Control Output & PLL Lock Time Capacitor LB_CONT SDO SDO Fig. 3 Serial Digital Output LF CP_CAP 300 27360-1 ...
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... GENNUM CORPORATION 27360-1 ...
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... GENNUM CORPORATION 27360-1 ...
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... GENNUM CORPORATION 27360-1 ...
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... A 2x1 input multiplexer is also provided for these signals. The internal carrier_detect signal is determined by the setting of the IP_SEL pin and is used by the lock detect block of the GS1560A to determine the lock status of the device, (see section 3.6.1). 3.2.3 Single Input Configuration If the application requires a single differential input, the second set of inputs may be left unconnected ...
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... DC supplied via the CP_VDD / CP_GND pins to provide +2. the VCO_VCC / VCO_GND pins. The control voltage to the VCO is output from the GS1560A on the LF pin and requires 4.7kΩ pull-up and pull-down resistors to ensure correct operation. The GO1525 produces a 1.485GHz reference signal for the reclocker, input on the VCO pin of the GS1560A ...
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... MODES OF OPERATION 3.6 MODES OF OPERATION 3.6 MODES OF OPERATION 3.6 MODES OF OPERATION The GS1560A has two basic modes of operation which determine how the lock detect block controls the integrated reclocker. Master mode is enabled when the application layer sets the MASTER/SLAVE pin HIGH, and slave mode is enabled when MASTER/SLAVE is set LOW ...
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... Master Mode Recall that the GS1560A is said master mode when the MASTER/SLAVE input signal is set HIGH. In this case, the following four device pins become output status signals: • SMPTE_BYPASS • DVB_ASI • SD/HD • RC_BYP The combined setting of these four pins will indicate whether the device has locked to valid SMPTE or DVB-ASI data rates ...
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... SMPTE FUNCTIONALITY 3.7 SMPTE FUNCTIONALITY 3.7 SMPTE FUNCTIONALITY The GS1560A is said SMPTE mode once the device has detected SMPTE TRS sync words and locked to the input data stream as described in section 3.6.1. The device will remain in SMPTE mode until such time that SMPTE TRS sync words fail to be detected ...
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... Table 4 may not correspond directly to the digital line counts. NOTE 2: Unless indicated by SMPTE 352M payload identifier packets, the GS1560A will not distinguish between 50/60 frames PsF and 25/30 frames interlaced for the 1125 line video systems; 24 PsF will be identified. ...
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... GENNUM CORPORATION SIGNAL PARALLEL SAMPLING STANDARD INTERFACE 4:2:2 274M 274M + 348M 296M 296M + 348M 4:2:2 BT.656 BT.656 + 305M 125M 125M + 305M 4:2:2 296M ...
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... HVF Timing Signal Generation The GS1560A extracts critical timing parameters from either the received TRS signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator (FW_EN/DIS = HIGH). Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F) timing are all extracted and presented to the application layer via the H:V:F status output pins ...
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... LUMA DATA OUT SIGNAL TIMING: H_CONFIG = LOW F H_CONFIG = HIGH PCLK MULTIPLEXED 3FF 000 Y/Cr/Cb DATA OUT GENNUM CORPORATION XYZ 000 (eav) XYZ 000 (eav) HVF TIMING - HDTV 20-BIT OUTPUT MODE 3FF 000 000 000 H:V:F TIMING AT EAV - HD 10-BIT OUTPUT MODE 3FF 000 ...
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... DVB-ASI FUNCTIONALITY 3.8 DVB-ASI FUNCTIONALITY 3.8 DVB-ASI FUNCTIONALITY 3.8 DVB-ASI FUNCTIONALITY The GS1560A is said DVB-ASI mode once the device has detected 32 consecutive DVB-ASI words without a single word or disparity error being generated. The device will remain in DVB-ASI mode until 32 consecutive DVB-ASI word or disparity errors are detected, or until SMPTE TRS ID words have been detected ...
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... Y/Cr/Cb DATA OUT FIFO_LD 3.10.2 Ancillary Data Detection and Indication The GS1560A will detect all types of ancillary data in either the vertical or horizontal blanking spaces and indicate via the status signal output pins YANC and CANC the position of ancillary data in the output data stream. These status ...
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... CANC PCLK LUMA DATA OUT BLANK CHROMA DATA OUT 000 YANC CANC PCLK MULTIPLEXED 000 3FF Y/Cr/Cb DATA OUT YANC/CANC GENNUM CORPORATION DID DC 3FF DBN DC 3FF DID DBN ANC DATA DETECTION - HD 20BIT OUTPUT MODE 3FF 3FF 3FF 3FF ANC DATA DETECTION - HD 10BIT OUTPUT MODE Fig ...
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... DID value, regardless of the SDID. In the case where all five DID and SDID values are set to zero, the GS1560A will detect all ancillary data types. This is the default setting after device reset or power-up. Where one or more, but less than five, DID and/or SDID values have been programmed, then only those matching ancillary data types will be detected and indicated ...
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... SMPTE 352M Payload Identifier The GS1560A can receive and detect the presence of the SMPTE 352M payload identifier ancillary data packet. This four word payload identifier packet may be used to indicate the transport mechanism, frame rate and line scanning / sampling structure. Upon reception of this packet, the device will extract the ...
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... The VD_STD[4:0], STD_LOCK and INT_PROG bits of the VIDEO_STANDARD register will default to zero after device reset or power up. These bits will also default to zero if the device loses lock to the input data stream, (LOCKED = LOW the SMPTE_BYPASS pin is asserted LOW. GENNUM CORPORATION NAME DESCRIPTION Not Used VD_STD[4:0] ...
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... ITU-R BT.656 1440x576/50 (2:1) (SD) (Or dual link progressive) 1Ah 625-line generic (EM) 1Dh Unknown HD 1Eh Unknown SD 1Ch, 1Fh GENNUM CORPORATION LENGTH VIDEO FORMAT OF HANC 358 198 2008 408 688 240 2668 492 2833 513 268 ...
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... Eh Fh 3.10.5 Error Detection and Indication The GS1560A contains a number of error detection functions to enhance operation of the device when operating in SMPTE mode. These functions, (except lock error detection), will not be available in either DVB-ASI or Data-Through operating modes (see sections 3.8 and 3.9). The device maintains an error status register at address 000 called ERROR_STATUS (Table 11) ...
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... YCRC_ERR 2 LNUM_ERR 1 SAV_ERR 0 EAV_ERR GENNUM CORPORATION DESCRIPTION Not Used Video Standard Error Flag. Set HIGH when a mismatch between the received SMPTE352M packets and the calculated video standard occurs. Full Field CRC Error Flag. Set HIGH in SD mode when a Full Field (FF) CRC mismatch has been detected in Field ...
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... EAV_ERR_MASK 3.10.5.1 Video Standard Error Detection If a mismatch between the received SMPTE 352M packets and the calculated video standard occurs, the GS1560A will indicate a video standard error by setting the VD_STD_ERR bit of the ERROR_STATUS register HIGH. 3.10.5.2 EDH CRC Error Detection The GS1560A calculates Full Field (FF) and Active Picture (AP) CRC words according to SMPTE RP165 in support of Error Detection and Handling packets in SD signals ...
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... Address: 024h 9-0 FF_LINE_START_F1[9:0] FF_LINE_END_F1 15-10 Address: 025h 9-0 FF_LINE_END_F1[9:0] GENNUM CORPORATION NAME DESCRIPTION Not Used Field 0 Active Picture start line data used to set EDH calculation range outside of SMPTE RP 165 values. Not Used Field 0 Active Picture end line data used to set EDH calculation range outside of SMPTE RP 165 values ...
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... This is accomplished via the ANC_TYPE register as described in section 3.10.2.1. 3.10.5.5 Line Based CRC Error Detection The GS1560A will calculate line based CRC words for HD video signals for both the Y and C data channels. These calculated CRC values are compared with the received CRC values and any mismatch is flagged in the YCRC_ERR and/or CCRC_ERR bits of the ERROR_STATUS register ...
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... TRS_INS 3.10.6.1 Illegal Code Remapping If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the GS1560A will remap all codes within the active picture between the values of 3FCh and 3FFh to 3FBh. All codes within the active picture area between the values of 000h and 003h will be re-mapped to 004h ...
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... One set of flags is provided for both fields 1 and 2. Field 1 flag data will be overwritten by field 2 flag data. NOTE: The GS1560A will detect EDH flags, but will not update the flags if an EDH CRC error is detected. Gennum's GS1532 Multi-Rate Serializer allows the host to individually set EDH flags ...
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... Parallel Output in Data-Through Mode t OD When operating in Data-Through mode, (see section 3.9), the GS1560A presents data to the output data bus without performing any decoding, descrambling or word-alignment. As described in section 3.9, the data bus outputs will be forced to logic LOW if the device is set to operate in master mode but cannot identify SMPTE TRS ID or DVB-ASI sync words in the input data stream ...
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... Parallel Output Clock (PCLK) The frequency of the PCLK output signal of the GS1560A is determined by the output data format. Table 16 below lists the possible output signal formats and their corresponding TABLE 16: Parallel Data Output Format OUTPUT DATA FORMAT 20bit/10bit 20bit DEMULTIPLEXED SD HIGH 10bit MULTIPLEXED SD ...
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... SDOUT 12ns following the falling edge of the LSB of the command word, and thus may be read by the host on the very next rising edge of the clock. The remaining bits are clocked out by the GS1560A on the negative edges of SCLK. t ...
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... DEVICE POWER UP 3.14 DEVICE POWER UP 3.14 DEVICE POWER UP 3.14 DEVICE POWER UP Because the GS1560A is designed to operate in a multi-volt environment, any power up sequence is allowed. The charge pump, phase detector, core logic, serial digital input / output buffers and digital I/O buffers should all be powered up within 1ms of one another. ...
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... 6.4n SDI GENNUM CORPORATION 10n CLI ...
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... GENNUM CORPORATION ...
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... Definition of Vertical Interval Switching Point for Synchronous Video Switching 6. PACKAGE & ORDERING INFORMATION 6. PACKAGE & ORDERING INFORMATION 6. PACKAGE & ORDERING INFORMATION 6. PACKAGE & ORDERING INFORMATION 6.1 PACKAGE DIMENSIONS 6.1 PACKAGE DIMENSIONS 6.1 PACKAGE DIMENSIONS 6.1 PACKAGE DIMENSIONS GENNUM CORPORATION Table X CONTROL DIMENSIONS ARE IN MILLIMETERS. Table MIL LIME TE R MIN ...
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... ORDERING INFORMATION 6.2 ORDERING INFORMATION 6.2 ORDERING INFORMATION 6.2 ORDERING INFORMATION PART NUMBER PACKAGE GS1560ACF 80-pin LQFP 7. REVISION HISTORY 7. REVISION HISTORY 7. REVISION HISTORY 7. REVISION HISTORY VERSION ECR DATE 0 128756 March 2003 1 129161 April 2003 DOCUMENT IDENTIFICATION PRELIMINARY DATA SHEET The product preproduction phase and specifications are subject to change without notice ...