GS1560A Gennum Corporation, GS1560A Datasheet - Page 46

• Manufacturer Part Number: GS1560A
• Description: Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
• Manufacturer: Gennum Corporation

Table 14: Host Interface Description for Internal Processing Disable Register
3.10.6.1 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE
register is set LOW, the GS1560A will remap all codes
within the active picture between the values of 3FCh and
3FFh to 3FBh. All codes within the active picture area
between the values of 000h and 003h will be re-mapped to
004h.
In addition, 8-bit TRS and ancillary data preambles will be
remapped to 10-bit values if this feature is enabled.
3.10.6.2 EDH CRC Error Correction
The GS1560A will generate and insert active picture and full
field CRC words into the EDH data packets received by the
device. This feature is only available in SD mode and is
enabled
IOPROC_DISABLE register LOW.
EDH CRC calculation ranges are described in section
3.10.5.2.
NOTE: Although the GS1560A will modify and insert EDH
CRC words and EDH packet checksums, EDH error flags
will not be updated by the device.
GENNUM CORPORATION
IOPROC_DISABLE
REGISTER NAME
Address: 000h
by
setting
the
15-9
BIT
8
7
6
5
4
3
2
1
0
EDH_CRC_INS
ILLEGAL_REMAP
ANC_CSUM_INS
EDH_CRC_INS
H_CONFIG
LNUM_INS
BIT NAME
CRC_INS
TRS_INS
bit
Horizontal sync timing output configuration. Set LOW for
active line blanking timing. Set HIGH for H blanking
based on the H bit setting of the TRS words. See Figure
8.
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable. The
IOPROC_EN/DIS pin must be set HIGH.
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction insertion. In SD mode set
HIGH to disable. The IOPROC_EN/DIS pin must be set
HIGH.
Ancillary Data Check-sum insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
Y and C line based CRC insertion. In HD mode, inserts
line based CRC words in both the Y and C channels.
Set HIGH to disable. The IOPROC_EN/DIS pin must be
set HIGH.
Y and C line number insertion. In HD mode set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
Timing Reference Signal Insertion. Set HIGH to disable.
The IOPROC_EN/DIS pin must be set HIGH.
of
the
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3.10.6.3 Ancillary Data Checksum Error Correction
When ancillary data checksum error correction and
insertion is enabled, the GS1560A will generate and insert
ancillary data checksums for all ancillary data words by
default. Where user specified ancillary data has been
programmed into the device (see section 3.10.2.1), only the
checksums for the programmed ancillary data types will be
corrected.
This feature is enabled when the ANC_CSUM_INS bit of the
IOPROC_DISABLE register is set LOW.
3.10.6.4 Line Based CRC Correction
The GS1560A will generate and insert line based CRC
words into both the Y and C channels of the data stream.
This feature is only available in HD mode and is enabled by
setting the CRC_INS bit of the IOPROC_DISABLE register
LOW.
DESCRIPTION
Not Used
Not Used
Not Used
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
27360-1
0
0
0
0
0
0
0