GS1560A Gennum Corporation, GS1560A Datasheet - Page 49

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GS1560A

Manufacturer Part Number
GS1560A
Description
Reclocking Deserializer For HD-SDI, Sd-sdi & Dvb-asi With Loop Thru Cable Driver. 3.3/1.8V Supply.
Manufacturer
Gennum Corporation
Datasheet

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3.11.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS1560A is
determined by the output data format. Table 16 below lists
the possible output signal formats and their corresponding
TABLE 16: Parallel Data Output Format
3.12 GSPI HOST INTERFACE
3.12 GSPI HOST INTERFACE
3.12 GSPI HOST INTERFACE
3.12 GSPI HOST INTERFACE
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire
interface provided to allow the host to enable additional
features of the device and /or to provide additional status
information through configuration registers in the GS1560A.
The GSPI comprises a serial data input signal SDIN, serial
data output signal SDOUT, an active low chip select CS,
and a burst clock SCLK.
Because these pins are shared with the JTAG interface
port, an additional control signal pin JTAG/HOST is
provided. When JTAG/HOST is LOW, the GSPI interface is
enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS
signals are provided by the host interface. The SDOUT pin
is a high-impedance output allowing multiple devices to be
GENNUM CORPORATION
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
20bit DEMULTIPLEXED HD
10bit MULTIPLEXED HD
10bit DVB-ASI
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
20bit DEMULTIPLEXED HD
10bit MULTIPLEXED HD
*NOTE1: Recall that SD/HD, SMPTE_BYPASS, and DVB_ASI are input control pins in slave mode to be set by the application layer, but
are output status signals set by the device in master mode.
**NOTE2: Data-Through mode is only available in slave mode (see section 3.9).
OUTPUT DATA FORMAT
20bit/10bit
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
STATUS / CONTROL SIGNALS*
SD/HD
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
DATA-THROUGH MODE**
SMPTE_BYPASS
DVB-ASI MODE
SMPTE MODE
49 of 55
HIGH
LOW
LOW
parallel clock rates. Note that DVB-ASI output will always be
in 10-bit format, regardless of the setting of the 20bit/10bit
pin.
connected in parallel and selected via the CS input. The
interface is illustrated in the Figure 13 below.
All read or write access to the GS1560A is initiated and
terminated by the host processor. Each access always
begins with a 16-bit command word on SDIN indicating the
address of the register of interest. This is followed by a 16-
bit data word on SDIN in write mode, or a 16-bit data word
on SDOUT in read mode.
DVB_ASI
HIGH
LOW
LOW
CHROMA
CHROMA
CHROMA
CHROMA
DVB-ASI
LUMA /
LUMA /
LUMA /
LUMA /
[19:10]
DOUT
LUMA
LUMA
LUMA
LUMA
DATA
CHROMA
CHROMA
CHROMA
CHROMA
FORCED
FORCED
FORCED
FORCED
FORCED
DOUT
LOW
LOW
LOW
LOW
LOW
[9:0]
74.25/1.001MHz
148.5/1.001MHz
74.25/1.001MHz
148.5/1.001MHz
13.5MHz
13.5MHz
74.25 or
148.5 or
74.25 or
148.5 or
27MHz
27MHz
27MHz
PCLK
27360-1

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