DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 124
DF2211NP24V
Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
1.DF2211NP24V.pdf
(756 pages)
- Current page: 124 of 756
- Download datasheet (5Mb)
I/O
P1DDR
RAM0
To change pin 14 from an output pin to an input pin, the value of bit 4 in P1DDR must be changed
from 1 to 0 (H'F0 to H'E0). Here the BCLR instruction will be used to clear bit 4 in P1DDR to 0.
I/O
P1DDR
RAM0
Since RAM0 is a read/write area of memory, performing the above bit manipulation using the
BCLR instruction causes only bit 4 in RAM0 to be cleared to 0. The value of RAM0 is then
written to P1DDR.
I/O
P1DDR
RAM0
By using the above procedure to access registers containing write-only bits, it is possible to create
programs that are not dependent on the type of instructions used.
Rev.7.00 Dec. 24, 2008 Page 70 of 698
REJ09B0074-0700
BCLR
MOV.B
MOV.B
#4,
@RAM0, R0L
R0L,
P17
Output
1
1
P17
Output
1
1
P17
Output
1
1
@RAM0
@P1DDR
P16
Output
1
1
P16
Output
1
1
P16
Output
1
1
P15
Output
1
1
P15
Output
1
1
P15
Output
1
1
P14
Output
1
1
P14
Output
1
0
P14
Input
0
0
P13
Input
0
0
P13
Input
0
0
P13
Input
0
0
P12
Input
0
0
P12
Input
0
0
P12
Input
0
0
P11
Input
0
0
P11
Input
0
0
P11
Input
0
0
P10
Input
0
0
P10
Input
0
0
P10
Input
0
0
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