DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 245

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
Figure 7.11 illustrates operation in block transfer mode when MARA is designated as a block area.
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit
is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to
the CPU. Figure 7.12 shows the operation flow in block transfer mode.
Address T
Address B
Notes:
Address T
Address T
Address B
Address B
A
A
Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 1)
L A = Value set in MARA
L B = Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
A
B
A
B
= L
= L
= L
= L
A
B
A
B
+ SAIDE · (–1)
+ DAIDE · (–1)
Block area
SAID
DAID
· (2
· (2
DTSZ
DTSZ
Consecutive transfer
of M bytes or words
is performed in
response to one
request
· (N–1))
· (M · N–1))
Transfer
Rev.7.00 Dec. 24, 2008 Page 191 of 698
1st block
2nd block
Nth block
REJ09B0074-0700
Address T
Address B
B
B

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