L64704 LSI Logic Corporation, L64704 Datasheet - Page 133

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

6.1
Synchronization
Scheme
Chapter 6
Decoding Pipeline
Synchronization
This chapter describes the configurable synchronization circuit that aligns
the decoding pipeline outputs to the overall frame structure of the
L64704. The decoding pipeline consists of the Viterbi Decoder, Deinter-
leaver, Reed-Solomon (RS) Decoder, and the Descrambler. This chapter
consists of four sections:
The L64704’s FEC synchronization scheme is composed of a three
stage synchronization process:
A global control module generates the control signals for the Viterbi,
Descrambler, Deinterleaver, and RS Decoder modules. The global con-
trol module handles the appropriate sequencing of the synchronization
signals for determining in- and out-of-synchronization. The input to the
FEC portion of the L64704 is two three-bit symbols generated by the
demodulator portion. The maximum information rate is 62.5 Mbits/s.
Section 6.1, “Synchronization Scheme,”
Decoding Pipeline three stage synchronization process.
Section 6.2, “Viterbi Decoder Synchronization,”
synchronization module for the Viterbi Decoder.
Section 6.3, “Reed-Solomon Deinterleaver Synchronization,”
the synchronization process for the Reed-Solomon Deinterleaver.
Section 6.4, “Descrambler Synchronization,”
nization module for the Descrambler module.
The first stage synchronization uses output statistics from the Viterbi
Decoder module.
The second stage identifies a synchronization word.
The third stage identifies an inverting synchronization word.
provides an overview of the
describes the synchro-
describes the
shows
6-1