L64704 LSI Logic Corporation, L64704 Datasheet - Page 194

• Manufacturer Part Number: L64704
• Description: Satellite Decoder Technical Manual 5/97
• Manufacturer: LSI Logic Corporation

Table B.3
QPSK
Demodulator Loop
Registers
B.2.3
Carrier Loop
B-6
Mnemonic
CLK_LCF
CLK_NF[15:0]
CLK_RATIO[2:0] Clock Ratio
Check that the clock frequency is not stuck at the rail, and that the op-
amp’s output voltage is not stuck at either 0 volts or the supply voltage.
The CLK_VCO_SWAP bit (Group 4, APR 14, bit 2) controls the polarity
of the CLK_VCOP/N signals.
To verify that the clock loop functions, trigger the ADC clock against the
BERT’s clock. If the clock loop is functioning normally, then the two
clocks are in phase.
The CLK_LCF status bit (Group 3, APR 9, bit 3) indicates whether the
clock loop is locked. The indication is for frequency lock and the flag
should be ON as soon as you finish programming the configuration
(Group 4) registers.
The layout of the board should keep the two pairs of
CAR_VCOxN and CAR_VCOxP, parallel and minimize the distance from
the L64704 output to the op-amp’s input. The following paragraphs out-
line a simple test to verify that the carrier loop functions:
L64704 Application Notes
Set the CAR_SW and CAR_OPEN bits in the Carrier Loop Configu-
ration register (Group 4, APR 33) to b11. This forces the sweep to
begin and disables the AFC.
–
–
Change the upper and lower sweep limits registers (CAR_USWL
and CAR_LSWL; Group 4, APR 29:32) and watch the prescaler
with a spectrum analyzer to see how the programmed values
control the sweep range.
Change the value in the Carrier Sweep Rate register
(CAR_SWR; Group 4, APR 28) to ensure that it is controlling the
sweep rate.
Description
Clock Frequency Lock Flag
Clock Loop Control Register 1
Clock Loop Control Register 2
Nominal Frequency of the Clock Input
Group
3
lines,
16:17
APR
14
15
18
9
Bit(s)
7:0
7:0
7:0
3